公开(公告)号：WO2017112396A1

公开(公告)日：2017-06-29

申请号：PCT/US2016/064955

申请日：2016-12-05

Applicant: INVENSAS CORPORATION

Inventor： SHEN, Hong ,  WANG, Liang ,  GAO, Gullian

IPC: H01L21/48 ,  H01L21/18 ,  H01L27/108 ,  H01L21/822

CPC classification number: H01L24/94 ,  H01L21/304 ,  H01L21/30625 ,  H01L21/31051 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76877 ,  H01L21/76898 ,  H01L21/78 ,  H01L24/32 ,  H01L24/83 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/32145 ,  H01L2224/83005 ,  H01L2224/83895 ,  H01L2224/83896 ,  H01L2225/06541 ,  H01L2924/10253 ,  H01L2924/1032 ,  H01L2924/1205 ,  H01L2924/1207 ,  H01L2924/1304 ,  H01L2924/1436

Abstract: Systems and methods for providing 3D wafer assembly with known-good- dies are provided. An example method compiles an index of dies on a semiconductor wafer and removes the defective dies to provide a wafer with dies that are all operational. Defective dies on multiple wafers may be removed in parallel, and resulting wafers with all good dies stacked in 3D wafer assembly. In an implementation, the spaces left by removed defective dies may be filled at least in part with operational dies or with a fill material. Defective dies may be replaced either before or after wafer-to-wafer assembly to eliminate production of defective stacked devices, or the spaces may be left empty. A bottom device wafer may also have its defective dies removed or replaced, resulting in wafer-to-wafer assembly that provides 3D stacks with no defective dies.

Abstract translation: 提供了用于提供具有已知良好模具的3D晶片组件的系统和方法。 示例方法编译半导体晶片上的裸片的索引并移除有缺陷的裸片以向晶片提供全部可操作的裸片。 可以并行移除多个晶片上的有缺陷的裸片，并且在3D晶片组件中堆叠具有所有良好裸片的所得晶片。 在一个实施方式中，被移除的有缺陷的模具留下的空间可以至少部分地用操作模具或填充材料填充。 可以在晶圆到晶圆组装之前或之后更换有缺陷的管芯，以消除有缺陷的堆叠器件的生产，或者空间可能被留空。 底部器件晶片也可能将其有缺陷的裸片移除或更换，从而导致提供没有缺陷裸片的3D堆叠的晶片 - 晶片组装。

公开(公告)号：WO2016077488A1

公开(公告)日：2016-05-19

申请号：PCT/US2015/060208

申请日：2015-11-11

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  TEXAS INSTRUMENTS JAPAN LIMITED

Inventor： LOPEZ, Osvaldo, Jorge ,  NOQUIL, Jonathan, Almeria ,  GREBS, Thomas, Eugene ,  MOLLOY, Simon, John

IPC: H01L25/03 ,  H01L23/02

CPC classification number: H01L25/0657 ,  H01L21/50 ,  H01L23/053 ,  H01L23/06 ,  H01L23/13 ,  H01L23/147 ,  H01L23/49844 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/071 ,  H01L25/074 ,  H01L25/18 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/06181 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/83851 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/00 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/04642 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/10155 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/1032 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1037 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1425 ,  H01L2924/1427 ,  H01L2924/15156 ,  H01L2924/157 ,  H01L2224/83

Abstract: In described examples, an electronic system includes a first chip (101) of single-crystalline semiconductor, including a first electronic device embedded in a second chip (102) of single-crystalline semiconductor shaped as a container having a slab (104) bordered by ridges (103), and including a second electronic device. The nested chips are assembled in a container of low-grade silicon shaped as a slab (130) bordered by retaining walls (131) and including conductive traces and terminals. The first electronic device is connected to the second electronic device by attaching the first chip onto the slab of the second chip. The first and second electronic devices are connected to the container by embedding the second chip in the container. The nested first and second chips operate as an electronic system, and the container operates as the package of the system. For first and second devices as field effect transistors, the system is a power block.

Abstract translation: 在所描述的实例中，电子系统包括单晶半导体的第一芯片（101），其包括第一电子器件，该第一电子器件嵌入在形成为容器的单晶半导体的第二芯片（102）中，该第一芯片（102）具有由 脊（103），并且包括第二电子设备。 嵌套的芯片组装在由保持壁（131）和包括导电迹线和端子邻接的平板（130）的低档硅形容器中。 第一电子设备通过将第一芯片附接到第二芯片的板上而连接到第二电子设备。 第一和第二电子设备通过将第二芯片嵌入容器而与容器相连。 嵌套的第一和第二芯片作为电子系统操作，并且容器作为系统的封装进行操作。 对于作为场效应晶体管的第一和第二器件，该系统是功率块。

公开(公告)号：WO2016036874A1

公开(公告)日：2016-03-10

申请号：PCT/US2015/048176

申请日：2015-09-02

Applicant: SKORPIOS TECHNOLOGIES, INC.

Inventor： LAMBERT, Damien ,  SPANN, John ,  KRASULICK, Stephen

IPC: H01L21/60

CPC classification number: H01L21/6835 ,  G02B6/4201 ,  H01L21/0274 ,  H01L21/2007 ,  H01L21/683 ,  H01L21/76254 ,  H01L24/03 ,  H01L24/27 ,  H01L24/75 ,  H01L24/83 ,  H01L24/89 ,  H01L24/94 ,  H01L24/95 ,  H01L2221/68313 ,  H01L2221/68318 ,  H01L2221/6834 ,  H01L2221/68354 ,  H01L2221/68368 ,  H01L2221/68381 ,  H01L2224/0362 ,  H01L2224/75305 ,  H01L2224/75315 ,  H01L2224/80201 ,  H01L2224/83001 ,  H01L2224/83203 ,  H01L2225/06593 ,  H01L2924/01014 ,  H01L2924/1032 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/15738

Abstract: A transfer substrate with a compliant resin is used to bond one or more chips to a target wafer. An implant region is formed in a transfer substrate. A portion of the transfer substrate is etched to form a riser. Compliant material is applied to the transfer substrate. A chip is secured to the compliant material, wherein the chip is secured to the compliant material above the riser. The chip is bonded to a target wafer while the chip is secured to the compliant material. The transfer substrate and compliant material are removed from the chip. The transfer substrate is opaque to UV light.

Abstract translation: 使用具有顺应性树脂的转印衬底将一个或多个芯片结合到目标晶片。 植入区域形成在转印衬底中。 转印衬底的一部分被蚀刻以形成提升器。 将合适的材料施加到转印基板上。 芯片被固定到柔性材料上，其中芯片被固定到提升管上方的柔性材料。 当芯片固定到顺应性材料时，芯片被结合到目标晶片。 从芯片上去除转印衬底和柔顺材料。 转印衬底对UV光是不透明的。

公开(公告)号：WO2014171439A1

公开(公告)日：2014-10-23

申请号：PCT/JP2014/060682

申请日：2014-04-15

Applicant: 住友電気工業株式会社

Inventor： 熊野　哲弥 ,  吉本　晋

IPC: H01L29/872 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/338 ,  H01L21/60 ,  H01L21/768 ,  H01L23/522 ,  H01L29/47 ,  H01L29/778 ,  H01L29/812

CPC classification number: H01L29/475 ,  H01L21/28581 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/89 ,  H01L29/778 ,  H01L29/812 ,  H01L29/872 ,  H01L2224/03002 ,  H01L2224/0345 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05075 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05644 ,  H01L2224/06051 ,  H01L2224/06181 ,  H01L2224/27002 ,  H01L2224/29017 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/32014 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48644 ,  H01L2224/73265 ,  H01L2224/80801 ,  H01L2224/83005 ,  H01L2224/83191 ,  H01L2224/83815 ,  H01L2224/92247 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01083 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/1032 ,  H01L2924/10323 ,  H01L2924/10325 ,  H01L2924/1033 ,  H01L2924/10334 ,  H01L2924/10341 ,  H01L2924/10344 ,  H01L2924/10346 ,  H01L2924/10355 ,  H01L2924/10356 ,  H01L2924/10357 ,  H01L2924/10358 ,  H01L2924/12032 ,  H01L2924/13064 ,  H01L2924/20106 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05124

Abstract: 　はんだ付半導体デバイス（１）は、基板（１０）と、基板（１０）上に配置された少なくとも１層のＩＩＩ族窒化物半導体層（２０）と、ＩＩＩ族窒化物半導体層（２０）上に配置されたショットキー電極（４０）と、ショットキー電極（４０）上に配置されたパッド電極（５０）と、を含む半導体デバイス（１Ｄ）を含み、パッド電極（５０）は少なくともＰｔ層を含む複層構造を有し、半導体デバイス（１Ｄ）のパッド電極（５０）上に配置された融点が２００℃以上２３０℃以下のはんだ（６０）をさらに含む。これにより、ショットキー電極と、その上に配置されたパッド電極と、その上に配置されたはんだとを含むはんだ付半導体デバイスについて、半導体デバイスの特性を低下させることなくそのはんだによる実装が可能なはんだ付半導体デバイスが提供される。

Abstract translation: 焊料附着的半导体器件（1）包括半导体器件（1D），其包括：衬底（10）; 设置在所述基板（10）上的至少一个III族氮化物半导体层（20）。 设置在所述III族氮化物半导体层上的肖特基电极; 以及设置在肖特基电极（40）上的焊盘电极（50），所述焊盘电极（50）具有至少包含Pt层的多层结构。 焊料附着的半导体器件还包括设置在半导体器件（1D）的焊盘电极（50）上并具有200-230℃的熔点的焊料（60）。 因此，提供了可以使用焊料安装而不会劣化半导体器件特性的焊料附着半导体器件，所述焊料附着半导体器件包括肖特基电极，设置在电极上的焊盘电极和设置在焊盘电极上的焊料 。

公开(公告)号：WO2017052658A1

公开(公告)日：2017-03-30

申请号：PCT/US2015/052494

申请日：2015-09-25

Applicant: INTEL CORPORATION ,  NELSON, Don W. ,  MUELLER, Brennen ,  JUN, Kimin

Inventor： NELSON, Don W. ,  MUELLER, Brennen

IPC: H01L25/065 ,  H01L23/48

CPC classification number: H01L23/48 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/94 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/24145 ,  H01L2224/24146 ,  H01L2224/24147 ,  H01L2224/32145 ,  H01L2224/73209 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/81203 ,  H01L2224/92124 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1032 ,  H01L2924/1421 ,  H01L2924/1434 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/82

Abstract: Integrated stacked strata of function die islands are described on a semiconductor device. One example is a multiple die package that includes a base die with a plurality of metal layers over top side circuitry. A first small die is placed on the base die at a first level of the metal layers. A second small die is placed on the base die above the first small die at a second level of the metal layers. The package has a plurality of metal routing lines and vias within the metal layers to connect the first small die and the second small die to the base die and a package to cover the base die and the small dies together.

Abstract translation: 在半导体器件上描述了功能裸片岛的集成层叠层。 一个例子是多管芯封装，其包括在顶侧电路上具有多个金属层的基模。 在金属层的第一层上将第一小模具放置在基模上。 将第二个小模具放置在金属层的第二层上的第一小模具上方的基底模具上。 该封装在金属层内具有多个金属布线线和通孔，以将第一小型管芯和第二小型管芯连接到基底管芯，以及将基底管芯和小型管芯覆盖在一起的封装。

公开(公告)号：WO2014052476A2

公开(公告)日：2014-04-03

申请号：PCT/US2013/061722

申请日：2013-09-25

Applicant: ARIZONA BOARD OF REGENTS, A BODY CORPORATE OF THE STATE OF ARIZONA, ACTING FOR AND ON...

Inventor： HERBOTS, Nichole ,  BENNETT-KENNETT, Ross ,  MURPHY, Ashlee ,  HUGHES, Brett ,  ACHARYA, Ajjya ,  WATSON, Clarizza ,  CULBERTSON, Robert

IPC: H01L21/18

CPC classification number: H01L24/83 ,  H01L21/187 ,  H01L21/2007 ,  H01L21/76254 ,  H01L21/84 ,  H01L27/1203 ,  H01L31/048 ,  H01L51/0024 ,  H01L2224/83201 ,  H01L2924/10253 ,  H01L2924/1027 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/1032 ,  Y02E10/50

Abstract: Substrates may be bonded according to a method comprising contacting a first bonding surface of a first substrate with a second bonding surface of a second substrate to form an assembly; and compressing the assembly in the presence of an oxidizing atmosphere under suitable conditions to form a bonding layer between the first and second surfaces, wherein the first bonding surface comprises a polarized surface layer; the second bonding surface comprises a hydrophilic surface layer; the first and second bonding surfaces are different.

Abstract translation: 可以根据包括使第一基板的第一接合表面与第二基板的第二接合表面接触以形成组件的方法来接合基板; 以及在合适的条件下在氧化气氛的存在下压缩所述组件以在所述第一和第二表面之间形成结合层，其中所述第一粘合表面包括极化表面层; 所述第二粘合表面包括亲水表面层; 第一和第二接合表面是不同的。

公开(公告)号：WO2012074571A1

公开(公告)日：2012-06-07

申请号：PCT/US2011/029568

申请日：2011-03-23

Applicant: TESSERA, INC. ,  OGANESIAN, Vage ,  HABA, Belgacem ,  MOHAMMED, Ilyas ,  MITCHELL, Craig ,  SAVALIA, Piyush

Inventor： OGANESIAN, Vage ,  HABA, Belgacem ,  MOHAMMED, Ilyas ,  MITCHELL, Craig ,  SAVALIA, Piyush

IPC: H01L23/48 ,  H01L25/065

CPC classification number: H01L25/00 ,  H01L21/76805 ,  H01L21/76898 ,  H01L23/3178 ,  H01L23/481 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/13025 ,  H01L2224/16225 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/29188 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/83005 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/10253 ,  H01L2924/1032 ,  H01L2924/1037 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2224/83 ,  H01L2924/00

Abstract: A microelectronic assembly 100 is provided in which first and second electrically conductive pads 108, 106 exposed at front surfaces of first and second microelectronic elements 110, 102, respectively, are juxtaposed, each of the microelectronic elements embodying active semiconductor devices. An electrically conductive element 114 may extend within a first opening 111 extending from a rear surface 118 of the first microelectronic element 110 towards the front surface 103 thereof, within a second opening 113 extending from the first opening 111 towards the front surface 103 of the first microelectronic element 110, and within a third opening 180 extending through at least one of the first and second pads 108, 106 to contact the first and second pads. Interior surfaces 121, 123 of the first and second openings 111, 113 may extend in first and second directions relative to the front surface 103 of the first microelectronic element 110, respectively, to define a substantial angle.

Abstract translation: 提供了微电子组件100，其中分别暴露在第一和第二微电子元件110,102的前表面处的第一和第二导电焊盘108,106并置，每个微电子元件体现有源半导体器件。 导电元件114可以在从第一微电子元件110的后表面118延伸到其前表面103的第一开口111内，在从第一开口111朝向第一开口111的前表面103延伸的第一开口113内延伸 微电子元件110，以及延伸穿过第一和第二焊盘108,106中的至少一个的第三开口180内，以接触第一和第二焊盘。 第一和第二开口111,113的内表面121,123可以分别相对于第一微电子元件110的前表面103在第一和第二方向上延伸，以限定大致的角度。

公开(公告)号：WO2012067992A2

公开(公告)日：2012-05-24

申请号：PCT/US2011/060553

申请日：2011-11-14

Applicant: TESSERA, INC. ,  HABA, Belgacem

Inventor： HABA, Belgacem

IPC: H01L23/498

CPC classification number: H01L24/05 ,  H01L23/49838 ,  H01L24/03 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L25/0657 ,  H01L2224/03001 ,  H01L2224/03003 ,  H01L2224/0311 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05551 ,  H01L2224/05552 ,  H01L2224/05555 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05576 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05686 ,  H01L2224/0569 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/16145 ,  H01L2224/16221 ,  H01L2224/29018 ,  H01L2224/29026 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1032 ,  H01L2924/10329 ,  H01L2924/1037 ,  H01L2924/1203 ,  H01L2924/12042 ,  H01L2924/1304 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1461 ,  H01L2924/20107 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An assembly 100 and method of making same are provided. The assembly 100 can include a first component 105 including a dielectric region 120 having an exposed surface 122, a conductive pad 134 at the surface 122 defined by a conductive element 132 having at least a portion extending in an oscillating or spiral path along the surface 122, and a an electrically conductive bonding material 140 joined to the conductive pad 134 and bridging an exposed portion 137 of the dielectric surface 122 between adjacent segments 136, 138. The conductive pad 134 can permit electrical interconnection of the first component 105 with a second component 107 having a terminal 108 joined to the pad 134 through the electrically conductive bonding material 140. The path of the conductive element 132 may or may not overlap or cross itself.

Abstract translation: 提供了组件100及其制造方法。 组件100可以包括第一部件105，第一部件105包括具有暴露表面122的电介质区域120，在表面122处的导电垫134由导电元件132限定，该导电元件132具有沿着表面122在振荡或螺旋路径中延伸的至少一部分 以及结合到导电焊盘134并桥接相邻段136,138之间的电介质表面122的暴露部分137的导电结合材料140.导电焊盘134可以允许第一部件105与第二部件 107，其具有通过导电结合材料140连接到焊盘134的端子108.导电元件132的路径可以重叠或不重叠。

公开(公告)号：WO2006031886A2

公开(公告)日：2006-03-23

申请号：PCT/US2005032743

申请日：2005-09-13

Applicant: INT RECTIFIER CORP ,  STANDING MARTIN ,  CLARKE ROBERT J

Inventor： STANDING MARTIN ,  CLARKE ROBERT J

IPC: H01L23/02

CPC classification number: H01L24/33 ,  H01L23/296 ,  H01L23/3107 ,  H01L23/4824 ,  H01L23/4951 ,  H01L23/49562 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/41725 ,  H01L29/4232 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/29611 ,  H01L2224/29644 ,  H01L2224/2969 ,  H01L2224/81054 ,  H01L2224/8121 ,  H01L2224/81224 ,  H01L2224/81815 ,  H01L2224/83815 ,  H01L2224/8384 ,  H01L2224/83851 ,  H01L2924/00011 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0715 ,  H01L2924/1032 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/186 ,  H01L2924/30101 ,  H01L2924/00 ,  H01L2224/29075 ,  H01L2924/00014

Abstract: A power semiconductor package that includes a semiconductor die having at least two power electrodes and a conductive clip electrically and mechanically coupled to each power electrode.

Abstract translation: 一种功率半导体封装，其包括具有至少两个功率电极的半导体管芯以及电连接和机械连接到每个功率电极的导电夹。

公开(公告)号：WO2017111865A1

公开(公告)日：2017-06-29

申请号：PCT/US2015/000486

申请日：2015-12-22

Applicant: INTEL CORPORATION

Inventor： KAMGAING, Telesphor ,  DOGIAMIS, Georgios, C. ,  NAIR, Vijay, K.

IPC: H01L23/66 ,  H01L23/28 ,  H01L25/065

CPC classification number: H01L23/66 ,  H01L23/5389 ,  H01L24/20 ,  H01L25/105 ,  H01L2223/6672 ,  H01L2223/6677 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/10253 ,  H01L2924/1032 ,  H01L2924/15192 ,  H01L2924/18162 ,  H01L2924/19011 ,  H01L2924/19104 ,  H01L2924/19105

Abstract: Embodiments of the invention include a microelectronic device that includes an overmolded component having a first die with a silicon based substrate. A second die is coupled to the first die with the second die being formed with compound semiconductor materials in a different substrate. A substrate is coupled to the first die. The substrate includes an antenna unit for transmitting and receiving communications at a frequency of approximately 4 GHz or higher.

Abstract translation: 本发明的实施例包括微电子器件，其包括具有带硅基衬底的第一管芯的包覆成型部件。 第二管芯耦合到第一管芯，第二管芯在不同衬底中用化合物半导体材料形成。 衬底耦合到第一管芯。 基板包括用于发射和接收大约4GHz或更高频率的通信的天线单元。