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111.发明授权A METHOD OF MANUFACTURING A MUTUAL CONNECTION STRUCTURE BETWEEN MULTI-LAYER BASEBOARDS AND STRUCTURE THEREOF 有权用于生产之间多层次的底板和结构及其相互联系结构
公开(公告)号：EP2120521B1
公开(公告)日：2016-01-27
申请号：EP07702269.7
申请日：2007-02-05
Applicant: Princo Corp.
Inventor： YANG, Chihkuang
CPC classification number: H05K1/117 , H01L21/4857 , H01L21/6835 , H01L23/5383 , H01L23/5385 , H01L24/16 , H01L2221/68318 , H01L2221/68345 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2924/00014 , H01L2924/01057 , H01L2924/01079 , H01L2924/01322 , H01L2924/14 , H01L2924/15159 , H05K1/142 , H05K3/0052 , H05K3/361 , H05K3/4611 , H05K2201/058 , H05K2201/091 , H05K2201/09109 , H05K2201/0919 , H01L2224/05599
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公开(公告)号：EP2877895A1
公开(公告)日：2015-06-03
申请号：EP13822993.5
申请日：2013-07-25
Applicant: E-Ink Corporation
Inventor： KAYAL, Matthew Joseph , BATTISTA, Stephen Joseph , PAOLINI, Richard J. Jr. , SUBRAMANIAN, Shyamala A.
IPC: G02F1/167
CPC classification number: G02F1/167 , B29D11/0073 , B32B37/12 , B32B38/0004 , B32B38/04 , B32B2307/202 , B32B2307/412 , B32B2310/0843 , B32B2457/20 , C09D11/52 , G02F1/133377 , G02F1/13439 , G02F1/1533 , G02F1/155 , G02F2201/42 , G02F2202/16 , G02F2202/28 , H05K1/0274 , H05K1/095 , H05K3/321 , H05K3/4053 , H05K3/4084 , H05K2201/0108 , H05K2201/091 , H05K2203/0455 , H05K2203/063
Abstract: Electrical connection between the backplane and the front electrode of an electro-optic display is provided by forming a front plane laminate (100) comprising, in order, a light-transmissive electrically-conductive layer (104), a layer of electro-optic material (106), and a layer of lamination adhesive (108); forming an aperture (114) through all three layers of the front plane laminate (100); and introducing a flowable, electrically-conductive material (118) into the aperture (114), the flowable, electrically-conductive material being in electrical contact with the light-transmissive electrically-conductive layer (104) and extending through the adhesive layer (108).
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113.发明公开A MUTUAL CONNECTION STRUCTURE BETWEEN MULTI-LAYER BOARDS AND MANUFACTURING METHOD THEREOF 审中-公开相互联系结构之间多层次板及其制造方法
公开(公告)号：EP2120517A4
公开(公告)日：2015-05-27
申请号：EP07702270
申请日：2007-02-05
Applicant: PRINCO CORP
Inventor： YANG CHIHKUANG
CPC classification number: H05K1/142 , H01L21/4857 , H01L23/5383 , H01L23/5385 , H01L24/19 , H01L24/82 , H01L2224/04105 , H01L2224/12105 , H01L2924/01005 , H01L2924/01006 , H01L2924/01018 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01322 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/15312 , H01L2924/19107 , H05K1/117 , H05K3/0052 , H05K3/361 , H05K3/4611 , H05K2201/058 , H05K2201/091 , H05K2201/09109 , H05K2201/0919 , H01L2924/00
Abstract: A hybrid structure of multi-layer substrates comprises a first multi-layer substrate and a second multi-layer substrate. The first multi-layer substrate stacks up first metal layers, first dielectric layers alternately and has VIAs. A border district of a first metal layer connects with a border district of the corresponding first dielectric layer. The border districts are separated from adjacent first metal layers and adjacent first dielectric layers. The second multi-layer substrate stacks up second metal layers and second dielectric layers alternately. A border district of a second metal layer connects with a border district of the corresponding second dielectric layer. The border districts are separated from adjacent second metal layers and adjacent second dielectric layers. The VIAs are located at the border districts of the first dielectric layers and each VIA has electric conductor therein to connect one first metal layer with one second metal layer.
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114.发明授权VERFAHREN ZUR HERSTELLUNG EINES VERDRAHTUNGSSUBSTRATS EINES HALBLEITERBAUTEILS MIT AUSSENKONTAKTANSCHLUSSFLECKEN FÜR AUSSENKONTAKTE 有权方法布线基板的半导体元件与国外连接接触PATCH外部联系人的生产
公开(公告)号：EP1779428B1
公开(公告)日：2015-05-27
申请号：EP05770056.9
申请日：2005-07-20
Applicant: Infineon Technologies AG
Inventor： BAUER, Michael , STEINER, Rainer , WÖRNER, Holger
IPC: H01L23/498 , H01L23/00 , H05K1/02 , H05K1/11
CPC classification number: H05K1/111 , H01L23/49811 , H01L23/49816 , H01L23/562 , H01L24/48 , H01L24/73 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2224/16237 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/73265 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/15173 , H01L2924/15311 , H01L2924/181 , H05K1/0271 , H05K1/114 , H05K2201/0133 , H05K2201/0187 , H05K2201/0355 , H05K2201/091 , H05K2203/0278 , Y02P70/611 , H01L2924/00012 , H01L2924/00 , H01L2224/05599 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/0555 , H01L2224/0556
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公开(公告)号：EP2229280B1
公开(公告)日：2015-02-11
申请号：EP08859872.7
申请日：2008-12-01
Applicant: Hewlett-Packard Development Company, L.P.
Inventor： DORAN, John
IPC: B41J2/175
CPC classification number: B41J2/17546 , B41J2/1753 , B41J2/17553 , H05K1/0269 , H05K1/0393 , H05K3/0064 , H05K2201/09063 , H05K2201/091 , H05K2203/163
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Patent Agency Ranking
公开(公告)号：EP2342957B1
公开(公告)日：2014-03-05
申请号：EP09793336.0
申请日：2009-10-07
Applicant: Molex Incorporated
Inventor： PANELLA, Augusto P. , BAINES, Elliot A. , LIN, Jeng-De
CPC classification number: H04Q1/136 , H04L41/12 , H05K1/118 , H05K1/144 , H05K1/147 , H05K3/326 , H05K2201/0311 , H05K2201/042 , H05K2201/09063 , H05K2201/09072 , H05K2201/091 , H05K2201/09445 , H05K2201/10189
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117.发明公开A METHOD OF MANUFACTURING A MUTUAL CONNECTION STRUCTURE BETWEEN MULTI-LAYER BASEBOARDS AND STRUCTURE THEREOF 有权用于生产之间多层次的底板和结构及其相互联系结构
公开(公告)号：EP2120521A4
公开(公告)日：2013-01-02
申请号：EP07702269
申请日：2007-02-05
Applicant: PRINCO CORP
Inventor： YANG CHIHKUANG
CPC classification number: H05K1/117 , H01L21/4857 , H01L21/6835 , H01L23/5383 , H01L23/5385 , H01L24/16 , H01L2221/68318 , H01L2221/68345 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2924/00014 , H01L2924/01057 , H01L2924/01079 , H01L2924/01322 , H01L2924/14 , H01L2924/15159 , H05K1/142 , H05K3/0052 , H05K3/361 , H05K3/4611 , H05K2201/058 , H05K2201/091 , H05K2201/09109 , H05K2201/0919 , H01L2224/05599
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公开(公告)号：EP2397587B1
公开(公告)日：2012-12-12
申请号：EP11160536.6
申请日：2011-03-30
Applicant: FUJITSU LIMITED
Inventor： Morita, Yoshihiro , Ooi, Takahiro , Yamada, Tetsuro , Matsui, Akiko , Sugane, Mitsuhiko , Mukoyama, Takahide
CPC classification number: H05K1/0366 , D03D1/0088 , D03D15/0011 , D03D15/0088 , D10B2401/18 , D10B2505/02 , H05K1/024 , H05K1/0245 , H05K1/0248 , H05K2201/029 , H05K2201/091 , H05K2203/0195 , Y10T29/49124
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119.发明公开
公开(公告)号：EP2341583A4
公开(公告)日：2012-10-31
申请号：EP09821841
申请日：2009-04-24
Applicant: ASAHI DENKA KENKYUSHO CO LTD
Inventor： MIZOGUCHI MASANORI
CPC classification number: H05K3/326 , H01R12/718 , H05K1/118 , H05K1/147 , H05K3/306 , H05K3/363 , H05K3/365 , H05K2201/0367 , H05K2201/091 , H05K2201/0949 , H05K2201/10378 , H05K2201/1059
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120.发明公开Three-dimensional liquid crystal polymer multilayer circuit board including membrane switch and related methods 有权三维液晶聚合物多层印刷电路板用薄膜开关和相关的方法
公开(公告)号：EP2428971A1
公开(公告)日：2012-03-14
申请号：EP11009318.4
申请日：2009-01-16
Applicant: Harris Corporation
Inventor： Rendek, Louis Joseph Jr. , Shacklette, Lawrence Wayne , Jaynes, Paul Brian , Marvin, Philip Anthony
IPC: H01H13/704 , H05K3/00 , H01H13/705 , H01H13/06
CPC classification number: H01H13/704 , H01H11/00 , H05K1/0284 , H05K3/303 , H05K3/4614 , H05K3/4626 , H05K3/4632 , H05K2201/0141 , H05K2201/091 , Y10T29/49107 , Y10T29/4913
Abstract: An electronic device includes (45) a multilayer circuit board (53) having a non-planar three-dimensional shape defining a membrane switch recess (52) therein. The multilayer circuit board may include at least one pair of liquid crystal polymer (LCP) layers (50,51), and at least one electrically conductive pattern layer (46,47) on defining at least one each LCP layer (50,51), each membrane switch electrode adjacent the membrane switch recess to define a membrane switch. The electronic device may further include a compressible dielectric material filling the membrane switch recess. The electronic device may also include at least one spring member within the membrane (56) switch recess.
Abstract translation: 一种电子设备，包括：（45）具有多层电路板（53）的非平面三维形状限定一个膜片开关的凹部（52）在其中。 多层电路板可以包括至少一对液晶聚合物（LCP）层（50,51），以及至少一个导电图案层（46,47）上限定至少一个每个LCP层（50,51） 中，每个膜电极切换相邻薄膜开关凹部，以限定一个薄膜开关。 所述电子设备可以包括一个可压缩的而且介电材料填充的薄膜开关凹部。 因此，该电子设备可以包括所述膜（56）开关凹部内的至少一个弹簧构件。
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