公开(公告)号：EP1341231A2

公开(公告)日：2003-09-03

申请号：EP03250539.8

申请日：2003-01-29

Applicant: STMicroelectronics, Inc.

Inventor： Chiu, Anthony M. ,  Siegel, Harry Michael

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/3105

CPC classification number: H01L21/481 ,  H01L21/4857 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2224/73265 ,  H05K3/4652 ,  H05K3/4655 ,  H05K2201/0195 ,  H05K2201/09781 ,  H05K2201/09881 ,  H05K2203/0278 ,  H01L2924/00014

Abstract: A system and method is disclosed for providing mechanical planarization of a sequential build up substrate for an integrated circuit package. A planarization plate is placed in contact with an uneven external surface of a dielectric layer that covers underlying functional circuit elements and filler circuit elements. A heating element in the planarization plate flattens protruding portions of the external surface of the dielectric layer to create a flat external surface on the dielectric layer. After the flat external surface of the dielectric layer has cooled, it is then covered with a metal conductor layer. The method of the present invention increases the number of sequential buildup layers that may be placed on a sequential buildup substrate.

公开(公告)号：EP1318708A3

公开(公告)日：2003-06-18

申请号：EP03004268.3

申请日：1996-10-23

Applicant: IBIDEN CO., LTD.

Inventor： Kawamura, Yoichiro ,  Murase, Hideki ,  Asai, Motoo

IPC: H05K3/46 ,  H05K3/38

CPC classification number: H05K3/0094 ,  H05K3/382 ,  H05K3/384 ,  H05K3/4602 ,  H05K2201/0129 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/0212 ,  H05K2201/0347 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09881 ,  H05K2203/0773

Abstract: A build-up multilayer printed circuit board in which an interlaminar insulating layer and a conductor layer are alternately laminated on a surface of a wiring substrate (1) having a conductor circuit (4) and a through-hole (9), and the conductor layers are electrically connected to each other through a viahole formed in the interlaminar insulating layer, characterized in that a roughened layer (11) is formed on a conductor surface of an inner wall of the through-hole (9), and a resin filler (10) is filled in a through-hole (9) formed in the wiring substrate (1).

Abstract translation: 一种在具有导体电路（4）和通孔（9）的布线基板（1）的表面上交替层叠层间绝缘层和导体层的积层多层印刷电路板，并且导体 层通过形成在层间绝缘层中的通孔彼此电连接，其特征在于，在所述通孔（9）的内壁的导体表面上形成有粗糙层（11）和树脂填料（ 10）填充在形成在布线基板（1）中的通孔（9）中。

公开(公告)号：EP1314172A1

公开(公告)日：2003-05-28

申请号：EP01960431.3

申请日：2001-06-30

Applicant: Moeller GmbH ,  Schmitz, Gerd

Inventor： SCHMITZ, Gerd

IPC: H01C17/065

CPC classification number: H05K1/167 ,  H01C17/0652 ,  H05K1/0257 ,  H05K1/095 ,  H05K3/386 ,  H05K2201/0323 ,  H05K2201/09881 ,  H05K2203/1453 ,  Y10T29/49099

Abstract: The invention relates to an electronic assembly, in particular, for low power consumption electric switching devices such as low power contactors, time relays or the like. In order to provide protection against input current pulses, an ohmic resistor (6) is provided in the form of a resistive layer that is applied by pressing.

公开(公告)号：EP1197130B1

公开(公告)日：2003-05-21

申请号：EP00948103.7

申请日：2000-07-13

Applicant: International Business Machines Corporation

Inventor： LAUFFER, John ,  RUSSELL, David

IPC: H05K1/16 ,  H05K3/46 ,  H01F41/04

CPC classification number: H01F41/041 ,  H01F17/0033 ,  H05K1/095 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/0023 ,  H05K3/386 ,  H05K3/4069 ,  H05K3/4644 ,  H05K2201/0187 ,  H05K2201/0191 ,  H05K2201/0209 ,  H05K2201/0367 ,  H05K2201/086 ,  H05K2201/09563 ,  H05K2201/097 ,  H05K2201/09881 ,  H05K2203/0568 ,  H05K2203/1453 ,  H05K2203/1461 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49169 ,  Y10T428/24917 ,  Y10T428/2495 ,  Y10T428/24967 ,  Y10T428/24975

Abstract: Passive electrical components such as capacitors, resistors, inductors, transformers, filters and resonators are integrated into electrical circuits utilizing a process which maximizes the utilization of the planar surfaces of the substrates for high density placement of active components such as logic or memory integrated circuits. The passive components are integrated into a conventional circuit board utilizing a photoimageable dielectric material (20). The dielectric (20) is photoimaged and etched to provide one or more recesses or openings (26) for the passive devices, and photovias interconnecting the inputs and outputs of the integrated circuit board. The electronic structure comprising at least one of the passive devices integrated into a photoimaged dielectric (20) is described as well as the method of manufacturing the same.

公开(公告)号：EP1229772A1

公开(公告)日：2002-08-07

申请号：EP01948057.3

申请日：2001-07-17

Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

Inventor： SUZUMURA, Masaki ,  HASHIMOTO, Fumiaki

IPC: H05K3/20 ,  H05K1/02 ,  H05K1/03 ,  H05K3/22 ,  H05K7/20 ,  H01L23/12

CPC classification number: H05K1/056 ,  H01L2924/0002 ,  H05K1/0373 ,  H05K3/202 ,  H05K3/28 ,  H05K2201/0209 ,  H05K2201/09881 ,  Y10S428/901 ,  Y10T428/12514 ,  Y10T428/12556 ,  Y10T428/24917 ,  Y10T428/31681 ,  H01L2924/00

Abstract: A circuit board of the present invention comprises a composite resin and a metal plate, and the metal plate forms circuit patterns. The metal plate is preferably made of copper or copper alloys having excellent heat conductivity. The composite resin comprises 70 - 95 parts by weight of inorganic filler, and 5 - 30 parts by weight of a resin composition including a thermosetting resin and a hardener. The metal plate is surface roughened or treated to reinforce the adhesion at least at one surface contacting with the composite resin. In the circuit board of the present invention, the composite resin fills spaces between the circuit patterns, and the composite resin composition and the metal plate form a plane at the side of the metal plate for mounting components. In the circuit board of the present invention, since the resin composition including the inorganic filler is also present in the spaces between circuit patterns of a metal plate, its heat dissipation characteristic is extremely high, and it is suited as a circuit board for electronic apparatus containing heat generating parts such as power circuit.

Abstract translation: 本发明的电路板包括复合树脂和金属板，并且金属板形成电路图案。 金属板优选由具有优异导热性的铜或铜合金制成。 复合树脂包含70-95重量份的无机填料和5-30重量份的包含热固性树脂和硬化剂的树脂组合物。 金属板被表面粗糙化或处理以至少在与复合树脂接触的一个表面上增强粘合力。 在本发明的电路基板中，复合树脂填充电路图案之间的空间，复合树脂组合物和金属板在用于安装元件的金属板侧形成一个平面。 在本发明的电路基板中，由于含有无机填料的树脂组合物也存在于金属板的电路图案之间的空间中，其散热特性极高，因此适合作为电子设备的电路基板 包含发电部件如电源电路。

公开(公告)号：EP1022146A1

公开(公告)日：2000-07-26

申请号：EP99101065.3

申请日：1999-01-25

Applicant: YAMAHA CORPORATION

Inventor： Tsubakida, Hideaki ,  Toda, Koji ,  Miura, Michio

IPC: B41J2/395

CPC classification number: B41J2/395 ,  H05K3/108 ,  H05K3/28 ,  H05K2201/0195 ,  H05K2201/09881 ,  Y10T29/49021 ,  Y10T29/49117 ,  Y10T29/49155

Abstract: A fine pitch electrode is provided in which fine electrode lines are disposed at even intervals and with high precision, and which has improved productivity and quality. The fine-pitch electrode 11 comprises a plurality of fine electrode lines 12, each of which is coated around its periphery with a coating film which is made of an electrical insulator, and a sealing member 19 in which a plurality of the fine electrode lines 12 are disposed on a plane and which is molded so as to incorporate the fine electrode lines 12.

Abstract translation: 本发明提供一种细间距电极，其中细电极线以均匀的间隔并以高精度布置，并且其具有改善的生产率和质量。 微细间距电极11包括的细的电极线12复数，每个的所有其涂覆在其周边有涂层的薄膜的所有其由电绝缘体，并在其中一个密封部件19的细的电极线12的多元性 布置是在一个平面上并且所有这一切都被模制以便纳入细电极线12

公开(公告)号：EP0804061A4

公开(公告)日：2000-01-05

申请号：EP96907729

申请日：1996-03-29

Applicant: IBIDEN CO LTD

Inventor： YASUE TOSHIHIKO ,  HIRAMATSU YASUJI ,  YANO HIDEKI ,  ISHITANI YOSHIFUMI ,  KAWAMURA YOICHIRO ,  MURASE HIDEKI ,  SUZUKI AYUMI ,  KAWADE MASATO

IPC: H05K3/00 ,  H05K3/38 ,  H05K3/46

CPC classification number: H05K3/4661 ,  H05K3/0094 ,  H05K3/382 ,  H05K3/384 ,  H05K3/4602 ,  H05K2201/0129 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/0212 ,  H05K2201/0347 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09881 ,  H05K2203/0773

Abstract: A multilayered printed wiring board having a smooth surface, which can be improved in resolution, interlayer insulating property, or thermal shock resistance without lowering its peel strength even if its insulating resin layer is thin. In the printed wiring board in which the conductor circuits of upper and lower layers are electrically insulated from each other by means of the insulating resin layer, the insulating layer is constituted of a composite layer composed of a lower layer made of a heat-resistant resin which is hardly soluble in an acid or oxidizing agent and an upper layer made of a bonding agent for electroless plating composed of a heat-resistant resin and, as necessary, a recessed section formed between conductor circuits of the lower layer is filled with a resin to the level corresponding to the surfaces of the conductor circuits.

Abstract translation: 提供一种具有优异的分辨率，层间绝缘性能和耐冷热冲击性的多层印刷电路板，而不会在表面上形成不均匀性，并且即使树脂绝缘层的厚度较薄，也降低剥离强度。 本发明提出了一种多层印刷电路板，包括形成在基板上的下导体电路层，形成在下导体电路层上的树脂绝缘层，形成在树脂绝缘层上的上导体电路层和形成在树脂中的通孔 绝缘层，用于电连接下导体电路层和上导体电路层，其中树脂绝缘层由热固性树脂和热塑性树脂的复合层组成。

公开(公告)号：EP0805615A3

公开(公告)日：1999-08-11

申请号：EP97500004.3

申请日：1997-01-14

Applicant: Eurocir, S.A.

Inventor： Arola, Juan Llongueras

IPC: H05K3/28

CPC classification number: H05K1/0265 ,  H05K3/28 ,  H05K2201/0166 ,  H05K2201/098 ,  H05K2201/09881

Abstract: Over a base board (1) made of any appropriate electroinsulating material, such as a phenolic resin or an epoxy resin, are established the classic electroconductive track (2), characteristic in that said tracks (2) are covered by a dielectric layer of ink (4), such as a thermic, photopolymeric or ultraviolet ink, which furthermore fills the grooves or gaps (5) defined between the tracks, thereby increasing the dielectric coefficient existing within said grooves (5) up to levels which render the occurence of electric arcs between them impossible, particularly in adverse environments such as corrosive environment resulting from humid and saline conditions, etc.

公开(公告)号：EP0805615A2

公开(公告)日：1997-11-05

申请号：EP97500004.3

申请日：1997-01-14

Applicant: Eurocir, S.A.

Inventor： Arola, Juan Llongueras

IPC: H05K3/28

CPC classification number: H05K1/0265 ,  H05K3/28 ,  H05K2201/0166 ,  H05K2201/098 ,  H05K2201/09881

Abstract: Over a base board (1) made of any appropriate electroinsulating material, such as a phenolic resin or an epoxy resin, are established the classic electroconductive track (2), characteristic in that said tracks (2) are covered by a dielectric layer of ink (4), such as a thermic, photopolymeric or ultraviolet ink, which furthermore fills the grooves or gaps (5) defined between the tracks, thereby increasing the dielectric coefficient existing within said grooves (5) up to levels which render the occurence of electric arcs between them impossible, particularly in adverse environments such as corrosive environment resulting from humid and saline conditions, etc.

Abstract translation: 在由诸如酚醛树脂或环氧树脂的任何适当的电绝缘材料制成的基板（1）上建立了经典的导电轨道（2），其特征在于所述轨道（2）被墨水的介电层覆盖 （4），例如热敏，光聚合物或紫外线墨水，其还填充限定在轨道之间的凹槽或间隙（5），从而将存在于所述凹槽（5）内的介电系数增加到使得发生电 它们之间的弧线是不可能的，特别是在恶劣环境下，如潮湿和盐水条件等引起的腐蚀性环境下

公开(公告)号：EP0708459A1

公开(公告)日：1996-04-24

申请号：EP95113470.9

申请日：1995-08-28

Applicant: International Business Machines Corporation

Inventor： Fogel, Keith Edward ,  Hedrick, Jeffrey Curtis ,  Lewis, David Andrew ,  Simony, Eva E. ,  Viehbeck, Alfred ,  Whitehair, Stanley Joseph

IPC: H01F27/28

CPC classification number: H05K3/445 ,  H01F17/0006 ,  H05K1/056 ,  H05K3/4046 ,  H05K2201/09636 ,  H05K2201/09881 ,  H05K2201/10416

Abstract: Structures are described having vias with more than one electrical conductor at least one of which is a solid conductor which is formed by inserting the wire into the via in a substrate wherein the wire is attached to an electrically conductive plate which is spaced apart from the substrate by a spacer which leave a space between the substrate and plate. The space is filled with a dielectric material. The space with via between the conductor and via sidewall is filled with a dielectric material. The via is used for making transformers and inductors wherein one of the via conductors is used for inner windings and another of the via conductors is used for outer windings.

Abstract translation: 描述了具有多于一个电导体的通孔的结构，其中至少一个是通过将电线插入基板中的通孔而形成的固体导体，其中导线附接到与基板间隔开的导电板 通过在基板和板之间留下空隙的间隔件。 该空间填充有电介质材料。 在导体和通孔侧壁之间具有通孔的空间填充有电介质材料。 通孔用于制造变压器和电感器，其中通孔导体中的一个用于内部绕组，另一个通孔导体用于外部绕组。