公开(公告)号：EP2939507A4

公开(公告)日：2016-08-03

申请号：EP13866930

申请日：2013-12-12

Applicant: FCI ASIA PTE LTD

Inventor： RENGARAJAN MADHUMITHA ,  DE GEEST JAN ,  SMITH STEPHEN B ,  SERCU STEFAAN H

IPC: H05K3/40

CPC classification number: H05K1/116 ,  H05K1/0222 ,  H05K1/0251 ,  H05K2201/09636 ,  H05K2201/09718 ,  H05K2203/0207 ,  H05K2203/0242

公开(公告)号：EP1841297B1

公开(公告)日：2010-01-20

申请号：EP07005727.8

申请日：2007-03-20

Applicant: TDK Corporation

Inventor： Iwata, Masashi

IPC: H05K1/02 ,  H04B1/40 ,  H03H7/46

CPC classification number: H05K1/0243 ,  H03H7/463 ,  H03H9/725 ,  H03H2001/0085 ,  H04B1/0057 ,  H05K1/0298 ,  H05K1/112 ,  H05K1/181 ,  H05K2201/09627 ,  H05K2201/09636 ,  H05K2201/1003 ,  H05K2201/10083

公开(公告)号：EP1714531A2

公开(公告)日：2006-10-25

申请号：EP05713419.9

申请日：2005-02-14

Applicant: MOLEX INCORPORATED

Inventor： REGNIER, Kent, E. ,  BRUNKER, David, L. ,  OGBUOKIRI, Martin, U.

IPC: H05K1/11

CPC classification number: H05K1/0245 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/1903 ,  H05K1/0222 ,  H05K1/0251 ,  H05K1/115 ,  H05K3/429 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09609 ,  H05K2201/09636 ,  H05K2201/09718 ,  H05K2201/10189 ,  H01L2924/00

Abstract: A circuit board (200, 300, 400) design is disclosed that is useful in high speed differential signal applications uses either a via arrangement or a circuit trace exit structure. In the via arrangement, sets of differential signal pair vias (301, 303, 401, 402) and an associated ground (302) are arranged adjacent to each other in a repeating pattern. The differential signal vias (301, 303, 591) of each pair are spaced closer to their associated ground via (302a, 593a) than the spacing between the adjacent differential signal pair associated ground (302b, 593b) so that differential signal vias exhibit a preference for electrically coupling to their associated ground vias. The circuit trace exit structure involves the exit portions of the circuit traces (420, 550) of the differential signal vias (401, 402, 591) to follow a path where the traces then meet with and join to the transmission line portions (552) of the conductive traces.

公开(公告)号：EP3288078A1

公开(公告)日：2018-02-28

申请号：EP17187037.1

申请日：2017-08-21

Applicant: NICHIA CORPORATION

Inventor： GOTO, Akira ,  SUGIMOTO, Kunihito

IPC: H01L25/075 ,  H01L33/64 ,  H05K1/02

CPC classification number: H01L33/647 ,  F21V19/0025 ,  F21Y2115/10 ,  H01L25/0753 ,  H01L33/505 ,  H01L33/60 ,  H01L33/62 ,  H01L33/641 ,  H01L33/642 ,  H05K1/0204 ,  H05K1/0206 ,  H05K1/0298 ,  H05K1/0306 ,  H05K1/09 ,  H05K1/181 ,  H05K2201/0187 ,  H05K2201/09636 ,  H05K2201/10106 ,  H05K2201/10674

Abstract: A light emitting device includes a mounting board, a first light emitting element and a second light emitting element. The mounting board includes an insulator which includes a front face and a back face, a pair of front face wiring parts disposed on the front face of the insulator, a connection wiring part disposed on the front face of the insulator and spaced apart from the front face wiring parts, a pair of back face terminals disposed on the back face of the insulator, first interlayer wiring parts penetrating the insulator and electrically connecting the front face wiring parts and the back face terminals, and one or more second interlayer wiring parts embedded in the insulator to be in contact with the connection wiring part, and spaced apart from the back face terminals.

Abstract translation: 发光装置包括安装板，第一发光元件和第二发光元件。 安装板包括绝缘体，该绝缘体包括正面和背面，布置在绝缘体的正面上的一对正面布线部分，布置在绝缘体的正面上并与正面隔开的连接布线部分 布置在绝缘体的背面上的一对背面端子，贯穿绝缘体并且电连接正面布线部分和背面端子的第一层间布线部分以及嵌入在绝缘体背面上的一个或多个第二层间布线部分 绝缘体将与连接布线部分接触，并与背面端子间隔开。

公开(公告)号：EP2658353A1

公开(公告)日：2013-10-30

申请号：EP13164422.1

申请日：2013-04-19

Applicant: Canon Kabushiki Kaisha

Inventor： Hayashi, Seiji ,  Kondo, Takuya ,  Matsumoto, Shoji

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/16

CPC classification number: H05K1/0216 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/48227 ,  H05K1/0228 ,  H05K1/0242 ,  H05K1/0298 ,  H05K1/11 ,  H05K1/114 ,  H05K1/116 ,  H05K1/14 ,  H05K1/141 ,  H05K1/162 ,  H05K1/18 ,  H05K2201/0939 ,  H05K2201/09418 ,  H05K2201/09454 ,  H05K2201/09463 ,  H05K2201/09636 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10734

Abstract: First (111) and second (112) signal wiring patterns are formed in a first conductor layer (101). A first electrode pad (121) electrically connected to the first signal wiring pattern through a first via (131) and a second electrode pad (122) electrically connected to the second signal wiring pattern through a second via (132) are formed in a second conductor layer (102) as a surface layer. A third conductor layer (103) is disposed between the first conductor layer and the second conductor layer with an insulator (105) interposed between those conductor layers. A first pad (141,151,161,171) electrically connected to the first via is formed in the third conductor layer. The first pad includes an opposed portion (141a,151b,161c,171d) which overlaps the second electrode pad as viewed in a direction perpendicular to the surface of a printed board and which is opposed to the second electrode pad through intermediation of the insulator. This enables reduction of crosstalk noise caused between the signal wirings.

Abstract translation: 在第一导体层（101）中形成第一（111）和第二（112）信号布线图案。 通过第二通孔（132）通过第一通孔（131）和与第二信号布线图案电连接的第二电极焊盘（122）电连接到第一信号布线图案的第一电极焊盘（121） 导体层（102）作为表面层。 第三导体层（103）设置在第一导体层和第二导体层之间，绝缘体（105）插入在这些导体层之间。 电连接到第一通孔的第一焊盘（141,151,161,171）形成在第三导体层中。 第一焊盘包括与垂直于印刷电路板的表面的方向观察的与第二电极焊盘重叠并且通过绝缘体与第二电极焊盘相对的相对部分（141a，151b，161c，171d）。 这能够减少在信号布线之间引起的串扰噪声。

公开(公告)号：EP1841297A1

公开(公告)日：2007-10-03

申请号：EP07005727.8

申请日：2007-03-20

Applicant: TDK Corporation

Inventor： Iwata, Masashi

IPC: H05K1/02 ,  H04B1/40 ,  H03H7/46

CPC classification number: H05K1/0243 ,  H03H7/463 ,  H03H9/725 ,  H03H2001/0085 ,  H04B1/0057 ,  H05K1/0298 ,  H05K1/112 ,  H05K1/181 ,  H05K2201/09627 ,  H05K2201/09636 ,  H05K2201/1003 ,  H05K2201/10083

Abstract: A high frequency module (1) incorporates a layered substrate (200). The layered substrate has a bottom surface (200a) and a top surface (200b). Terminals (Rx11) are disposed on the bottom surface. SAW filters (121) and inductors (81) are mounted on the top surface. The layered substrate incorporates: a first conductor layer (433) connecting the SAW filters to the inductors; a second conductor layer (451) connected to the terminals and disposed at a location closer to the bottom surface than the first conductor layer; and a plurality of parallel signal paths (701,702) each of which is formed using at least one through hole (h25,h26) provided inside the layered substrate and each of which connects the first and second conductor layers to each other.

Abstract translation: 高频模块（1）结合了分层基板（200）。 分层基板具有底面（200a）和顶面（200b）。 终端（Rx11）放置在底部表面上。 SAW滤波器（121）和电感器（81）安装在顶面上。 分层基板包括：将SAW滤波器连接到电感器的第一导体层（433） 第二导体层（451），连接到所述端子并设置在比所述第一导体层更靠近所述底表面的位置处; 以及多个平行信号路径（701,702），每个平行信号路径使用设置在层叠基板内的至少一个通孔（h25，h26）形成，并且每个平行信号路径将第一和第二导体层彼此连接。

公开(公告)号：EP2779810A3

公开(公告)日：2014-11-26

申请号：EP14158757.6

申请日：2014-03-11

Applicant: Tripod Technology Corporation

Inventor： Huang, Bo-Shiung ,  Yang, Wei-Hsiung ,  Shih, Han-Ching ,  Lin, Cheng-Feng

IPC: H05K1/16 ,  H05K3/46 ,  H01F17/06 ,  H05K1/11 ,  H05K1/02 ,  H05K3/42

CPC classification number: H05K1/0271 ,  H01F17/0033 ,  H01F17/062 ,  H01F27/2804 ,  H05K1/165 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/029 ,  H05K2201/086 ,  H05K2201/09636 ,  H05K2203/1178 ,  Y10T29/49165

Abstract: A printed circuit board package structure includes a substrate (110) having a first surface (111) and a second surface (113), a ring-shaped magnetic element (120), an adhesive layer (130), conductive portions (140) and conductive channels (150). The first and second surfaces respectively have first (114) and second (116) metal portions. A ring-shaped concave portion (112) is formed on a position not covered by the first metal portions of the first surface. The ring-shaped magnetic element is placed in the ring-shaped concave portion. The adhesive layer covers the first metal portions and the ring-shaped magnetic element. The conductive portions are formed on the adhesive layer. The conductive channels penetrate the conductive portions, the adhesive layer, and the substrate, and are respectively located in an inner wall (122) and outside an outer wall (124) of the ring-shaped concave portion. Each of the conductive channels includes a conductive film (152) electrically connects to the aligned conductive portion and second metal portion.

公开(公告)号：EP2154747A1

公开(公告)日：2010-02-17

申请号：EP09167215.4

申请日：2009-08-04

Applicant: SELEX COMMUNICATIONS S.p.A.

Inventor： Russo, Massimo ,  Di Maggio, Francesco ,  Pomona, Ignazio

IPC: H01P5/08 ,  H05K1/02

CPC classification number: H05K1/0251 ,  H01P1/047 ,  H05K1/115 ,  H05K3/429 ,  H05K2201/09536 ,  H05K2201/09627 ,  H05K2201/09636

Abstract: Described herein is a device with vertical transition (1) having a plurality of layers set on top of one another, which define a first transmission line (2) and a second transmission line (3); the first transmission line (2) has a first conductive path (5) and the second transmission line (3) has a second conductive path (10); an electrical connection structure (20, 21) extends vertically through one or more of the layers set on top of one another and provides the connection between the first conductive path (5) and the second conductive path (10). The electrical connection structure (20, 21) generates a condition of resonance for a signal travelling in the first conductive path (5) and/or second conductive path (10) and having a frequency selected in a band of pre-set frequencies.

Abstract translation: 这里描述的是具有垂直转换（1）的装置，其具有设置在彼此之上的多个层，其限定第一传输线（2）和第二传输线（3）; 第一传输线（2）具有第一导电路径（5），第二传输线（3）具有第二导电路径（10）; 电连接结构（20,21）垂直延伸穿过设置在彼此之上的一层或多层，并提供第一导电路径（5）和第二导电路径（10）之间的连接。 电连接结构（20,21）产生在第一导电路径（5）和/或第二导电路径（10）中行进并且具有在预定频率的频带中选择的频率的信号的谐振条件。

公开(公告)号：EP1956615A3

公开(公告)日：2008-12-24

申请号：EP07254736.7

申请日：2007-12-07

Applicant: Renesas Technology Corp.

Inventor： Takahashi, Wataru ,  Tsuchida, Shigeru ,  Okabe, Hiroshi

IPC: H01F17/00 ,  H05K1/02 ,  H05K1/16 ,  H04B1/38 ,  H01L23/48 ,  H01L23/52 ,  H01L23/64

CPC classification number: H05K1/165 ,  H01F17/0006 ,  H01L2924/0002 ,  H03H7/0115 ,  H03H7/1758 ,  H03H7/1766 ,  H03H7/383 ,  H03H7/465 ,  H03H2001/0085 ,  H05K1/0237 ,  H05K1/116 ,  H05K1/16 ,  H05K3/429 ,  H05K2201/09636 ,  H05K2201/09672 ,  H01L2924/00

Abstract: A parallel resonant circuit is realized by stacking first to fourth wiring patterns (MS21,MS22,MS23,MS24) each having at least an inductance element. One of the adjacent first and second wiring patterns is set to a signal input node (Nin) and the other thereof is set to a signal output node (Nout). Then, the signal input node is connected to the signal output node via inductance elements of the first wiring pattern, third wiring pattern, fourth wiring pattern and second wiring pattern in order. By adjacently forming wiring layers of the signal input and output nodes, a capacitance value between the input and output nodes is increased compared to that when they are separated. Also, by increasing the line width of the first and second wiring patterns, the capacitance value can be further increased. Therefore, it is possible to achieve a large capacitance value in a small area and downsizing of the electronic device.

公开(公告)号：EP1269808A1

公开(公告)日：2003-01-02

申请号：EP01916828.5

申请日：2001-03-30

Applicant: DYCONEX PATENTE AG

Inventor： SCHMIDT, Walter

IPC: H05K3/40 ,  H05K3/46

CPC classification number: H01L23/49827 ,  H01L2924/0002 ,  H05K1/0263 ,  H05K1/0268 ,  H05K1/0272 ,  H05K1/0274 ,  H05K1/113 ,  H05K1/115 ,  H05K1/141 ,  H05K1/144 ,  H05K1/162 ,  H05K1/185 ,  H05K3/005 ,  H05K3/0055 ,  H05K3/0061 ,  H05K3/041 ,  H05K3/046 ,  H05K3/3436 ,  H05K3/368 ,  H05K3/4084 ,  H05K3/4602 ,  H05K3/4614 ,  H05K3/4641 ,  H05K3/4644 ,  H05K3/4652 ,  H05K2201/0379 ,  H05K2201/0394 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/09636 ,  H05K2201/0969 ,  H05K2201/09827 ,  H05K2201/10378 ,  H05K2201/10598 ,  H05K2203/0108 ,  H05K2203/0195 ,  H05K2203/0285 ,  H05K2203/095 ,  H05K2203/1189 ,  H05K2203/163 ,  Y02P70/613 ,  Y10T29/49155 ,  H01L2924/00

Abstract: According to the invention, a microperforation (PMP) process step is combined with the lamination process. To this end, a dielectric layer (11,11') and a prefabricated product (1) are placed between two perforation dies (21,23) or a support and a perforation die. The prefabricated product (1) is partially covered by a conducting layer forming structures to be contacted by microvias. Pressure is applied on the perforation die (21,22), perforation tips of the perforation dies forming microvias for contacting the structures. A surface of the dielectric layer (11,11') or the prefabricated product (1) is configurated or coated to in a manner that the prefabricated product (1) and the dielectric layer (11,11') stick to each other after the pressure has been applied.