公开(公告)号：EP1883120A2

公开(公告)日：2008-01-30

申请号：EP07112933.2

申请日：2007-07-23

Applicant: Gia Tzoong Enterprise Co. Ltd.

Inventor： Tseng, Chi-Li ,  Chang, Shang-Fu ,  Yeh, Tzu-Li

IPC: H01L33/00

CPC classification number: H05K1/0209 ,  G02F1/133603 ,  H01L33/62 ,  H01L33/64 ,  H01L2924/0002 ,  H05K1/0206 ,  H05K1/021 ,  H05K1/056 ,  H05K1/182 ,  H05K3/3452 ,  H05K3/4641 ,  H05K2201/0209 ,  H05K2201/09881 ,  H05K2201/10106 ,  H01L2924/00

Abstract: A liquid crystal display (LCD) has an LED substrate comprising a base layer (10), a heat conductive layer (11), an electrical conductive layer (12) and a light emitting diode (13). With the substrate, heat is well dissipated. The substrate can be easily manufactured. And, thus, the cost for the LCD is reduced.

Abstract translation: 液晶显示器（LCD）具有包括基层（10），导热层（11），导电层（12）和发光二极管（13）的LED基板。 对于基材，热量散发良好。 衬底可以很容易地制造。 因此，LCD的成本降低了。

公开(公告)号：EP1626420A3

公开(公告)日：2007-12-19

申请号：EP05017300.4

申请日：2005-08-09

Applicant: TDK Corporation

Inventor： Abe, Kyotaro ,  Ishiyama, Tamotsu ,  Sato, Shigeki

IPC: H01G4/30

CPC classification number: C04B35/6342 ,  C04B35/4682 ,  C04B35/6261 ,  C04B35/62625 ,  C04B35/6263 ,  C04B35/6264 ,  C04B35/62665 ,  C04B35/632 ,  C04B35/64 ,  C04B2235/3206 ,  C04B2235/3215 ,  C04B2235/3225 ,  C04B2235/3239 ,  C04B2235/3262 ,  C04B2235/3436 ,  C04B2235/3454 ,  C04B2235/5445 ,  C04B2235/6025 ,  C04B2235/6582 ,  C04B2235/663 ,  H01G4/308 ,  H05K1/0306 ,  H05K3/207 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/09881 ,  H05K2203/0156 ,  Y10T428/252

Abstract: A release layer paste used for producing a multilayer electronic device, used in combination with an electrode layer paste including terpineol, dehydroterpineol, terpineol acetate, or dehydroterpineol acetate and including a ceramic powder, organic vehicle, plasticizer, and dispersion agent, the organic vehicle containing a binder having polyvinyl acetal as its main ingredient, a ratio (P/B) of the ceramic powder and the binder and plasticizer being controlled to 1.33 to 5.56 (however, excluding 5.56).

公开(公告)号：EP1843650A2

公开(公告)日：2007-10-10

申请号：EP07013524.9

申请日：1999-07-30

Applicant: IBIDEN CO., LTD.

Inventor： Hirose, Naohiro ,  Noda, Kouta ,  Segawa, Hiroshi ,  En, Honjin ,  Tsukada, Kiyotaka ,  Ishida, Naoto ,  Asano, Kouji ,  Shouda, Atsushi

IPC: H05K3/46 ,  H05K3/38

CPC classification number: H05K3/4652 ,  B23K26/389 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/0201 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/0055 ,  H05K3/0094 ,  H05K3/108 ,  H05K3/28 ,  H05K3/381 ,  H05K3/383 ,  H05K3/384 ,  H05K3/427 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4661 ,  H05K2201/0195 ,  H05K2201/0352 ,  H05K2201/0358 ,  H05K2201/062 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09827 ,  H05K2201/09863 ,  H05K2201/09881 ,  H05K2203/0307 ,  H05K2203/0353 ,  H05K2203/0554 ,  H05K2203/0773 ,  H05K2203/107 ,  H05K2203/121 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: A multilayered printed circuit board comprising: a substrate (330) on which a conductive circuit (334) is formed; an interlayer insulating resin layer (350) formed on the conductive circuit (334); an opening (348) for forming a via hole (360) formed in the interlayer insulating resin layer (350); and another conductive circuit (358) including a via hole (360) and formed on the interlayer insulating resin layer (350), wherein
the surface of the conductive circuit (334) is subjected to a coarsening process using etching solution containing cupric complex and organic acid, and
stripe pits and projections are formed on the inner wall of the opening (348) for forming the via hole (360).

公开(公告)号：EP1549121A3

公开(公告)日：2007-09-26

申请号：EP04257925.0

申请日：2004-12-17

Applicant: TDK Corporation

Inventor： Abe, Toshiyuki ,  Suzuki, Yoshihiro ,  Katsumata, Masashi

IPC: H05K1/16 ,  H03F3/60 ,  H05K3/46

CPC classification number: H05K1/0265 ,  H01L2924/1423 ,  H03F3/195 ,  H03F2200/294 ,  H05K1/165 ,  H05K3/243 ,  H05K3/4644 ,  H05K2201/0352 ,  H05K2201/09736 ,  H05K2201/09881 ,  H05K2203/0542

Abstract: An inductor element containing circuit board (1) of the present invention comprises a plurality of conductive layers, and a conductor having an inductor function (inductor conductor segment, 21) in one or more of the conductive layers, wherein at least part of the inductor conductor segment (21) is made thicker than other conductors disposed within the circuit board (1). The at least part of the inductor conductor segment (21) extends through an insulating layer (11-17) disposed between the conductive layers, or is embedded in the insulating layer (11-17), wherein the part of the inductor conductor segment (21) has a thickness one-half or more the thickness of the insulating layer (11-17). A power amplifier module (100) of the present invention comprises the multi-layer circuit board (1), a semiconductor amplifier fabricated in the multi-layer circuit board (1), and an impedance matching circuit coupled to the output of the semiconductor amplifier. The impedance matching circuit has a portion thereof formed of the inductor conductor segment (21).

Abstract translation: 本发明的电感器元件（1）包括多个导电层，以及在一个或多个导电层中具有电感器功能（电感器导体段21）的导体，其中电感器的至少一部分 导体段（21）被制成比设置在电路板（1）内的其它导体更厚。 电感器导体段（21）的至少一部分延伸穿过设置在导电层之间的绝缘层（11-17），或者嵌入在绝缘层（11-17）中，其中电感器导体段 21）的厚度为绝缘层（11-17）的厚度的一半以上。 本发明的功率放大器模块（100）包括多层电路板（1），在多层电路板（1）中制造的半导体放大器，以及耦合到半导体放大器的输出的阻抗匹配电路 。 阻抗匹配电路的一部分由电感器导体段（21）形成。

公开(公告)号：EP1827067A2

公开(公告)日：2007-08-29

申请号：EP06255669.1

申请日：2006-11-03

Applicant: Agere Systems, Inc.

Inventor： Cohn, Charles

IPC: H05K3/24 ,  H01L23/498

CPC classification number: H05K1/111 ,  H01L23/49811 ,  H01L23/4985 ,  H01L2224/16225 ,  H05K1/0204 ,  H05K1/0393 ,  H05K1/189 ,  H05K3/064 ,  H05K3/202 ,  H05K3/243 ,  H05K3/3452 ,  H05K3/4007 ,  H05K2201/0355 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/09881 ,  H05K2201/10674 ,  H05K2203/016 ,  H05K2203/0376 ,  Y02P70/611

Abstract: A circuit substrate for attachment to an integrated circuit chip comprises an electrical trace, a mounting pad and a dielectric layer. The mounting pad has a first surface, one or more sidewalls and a second surface. The first surface is attached to the electrical trace. The dielectric layer substantially covers the one or more sidewalls of the mounting pad and has an uppermost surface that is substantially coplanar with the second surface of the mounting pad.

Abstract translation: 用于附接到集成电路芯片的电路基板包括电迹线，安装焊盘和介电层。 安装垫具有第一表面，一个或多个侧壁和第二表面。 第一个表面附着在电气痕迹上。 电介质层基本上覆盖安装焊盘的一个或多个侧壁，并且具有与安装焊盘的第二表面基本共面的最上表面。

公开(公告)号：EP1250031B1

公开(公告)日：2007-06-06

申请号：EP02252573.7

申请日：2002-04-10

Applicant: NGK INSULATORS, LTD.

Inventor： Ikeda, Koji, NGK Insulators Ltd., I.P.D. ,  Shibata, Kazuyoshi, NGK Insulators Ltd., I.P.D.

IPC: H05K1/16 ,  H05K3/46 ,  H01L41/047 ,  H01L41/24

CPC classification number: H05K3/38 ,  H01L41/047 ,  H01L41/0471 ,  H01L41/0477 ,  H01L41/094 ,  H01L41/273 ,  H01L41/29 ,  H01L41/314 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K1/16 ,  H05K3/4667 ,  H05K2201/0175 ,  H05K2201/09881 ,  H05K2201/10083 ,  H01L2924/00

Abstract: The board includes a ceramic substrate (112) and a wiring pattern (114) disposed as an electrode layer on the substrate. The wiring pattern has gaps (120) filled with an insulating layer (122) made of cermet. The cermet layer contains a material of the electrode layer. Independent claims are also included for the following: (a) a method of manufacturing a wiring board.

公开(公告)号：EP1791405A2

公开(公告)日：2007-05-30

申请号：EP07003852.6

申请日：2002-04-10

Applicant: NGK INSULATORS, LTD.

Inventor： Ikeda, Koji ,  Shibata, Kazuyoshi

IPC: H05K1/16 ,  H05K3/46 ,  H01L41/047 ,  H01L41/24

CPC classification number: H05K3/38 ,  H01L41/047 ,  H01L41/0471 ,  H01L41/0477 ,  H01L41/094 ,  H01L41/273 ,  H01L41/29 ,  H01L41/314 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K1/16 ,  H05K3/4667 ,  H05K2201/0175 ,  H05K2201/09881 ,  H05K2201/10083 ,  H01L2924/00

Abstract: A wiring board (110A) has a ceramic substrate (112) and a first wiring pattern (114) disposed on it, gaps (120) of the wiring pattern being filled with a cermet insulating layer (122). There may be a piezoelectric/electrostrictive layer (116) and a cermet second wiring pattern (118) successively.
In a method, a first cermet layer (130) to be the first wiring pattern (114) and a second cermet layer (132) to be the insulating layer (122) filling gaps (120) in the first wiring pattern (114) are formed on a ceramic substrate (112). Thereafter, the first cermet layer (130) and the second cermet layer (132) are fired to product the first wiring pattern (114) and the insulating layer (122) simultaneously. Then, a PZT paste (134) may be formed and thereafter fired to produce the piezoelectric/electrostrictive layer (116). Thereafter, a third cermet layer (136) may be formed and thereafter fired to produce the second wiring pattern (118).

Abstract translation: 布线基板（110A）具有陶瓷基板（112）和设置在其上的第一布线图案（114），该布线图案的间隙（120）填充有金属陶瓷绝缘层（122）。 可以依次存在压电/电致伸缩层（116）和金属陶瓷第二布线图案（118）。 在一种方法中，成为第一布线图案（114）的第一金属陶瓷层（130）和成为填充第一布线图案（114）中的间隙（120）的绝缘层（122）的第二金属陶瓷层（132）是 形成在陶瓷衬底（112）上。 此后，烧制第一金属陶瓷层（130）和第二金属陶瓷层（132）以同时产生第一布线图案（114）和绝缘层（122）。 然后，可以形成PZT糊剂（134），然后烧制以产生压电/电致伸缩层（116）。 此后，可以形成第三金属陶瓷层（136），然后烧制以产生第二布线图案（118）。

公开(公告)号：EP1053507B1

公开(公告)日：2007-04-11

申请号：EP99939643.5

申请日：1999-06-29

Applicant: MOTOROLA, INC.

Inventor： DUNN, Gregory, J. ,  SAVIC, Jovica ,  BEUHLER, Allyson

IPC: G03C5/00 ,  H05K1/16

CPC classification number: H05K1/167 ,  G03F7/00 ,  H01C17/07 ,  H05K3/0023 ,  H05K3/025 ,  H05K3/048 ,  H05K3/386 ,  H05K2201/0317 ,  H05K2201/09881 ,  H05K2203/0152 ,  H05K2203/1461

Abstract: A method for manufacturing a microelectronic assembly to have a resistor (12) on a circuit board (10). The method entails applying a photosensitive dielectric to a substrate (18) to form a dielectric layer. The dielectric layer is photoimaged to polymerize a first portion (22). An electrically resistive film (14) is then applied to the dielectric layer and the dielectric layer is developed so that a portion of the resistive film remains over the second portion to form the resistor. A second dielectric layer (32) is then applied, photoimaged and developed to form openings (34). Terminations (16) can then be formed in the openings by known plating techniques. The resistive film is preferably a multilayer film that includes an electrically resistive layer, such as NiP, NiCr or other nickel alloy and a sacrificial backing such as a layer of copper.

公开(公告)号：EP1395102A3

公开(公告)日：2007-03-14

申请号：EP03018683.7

申请日：2003-08-22

Applicant: KURARAY CO., LTD.

Inventor： Tsugaru, Toshinori, Kuraray Co., Ltd. ,  Sunamoto, Tatsuya, Kuraray Co., Ltd. ,  Yoshikawa, Tadao, Kuraray Co., Ltd.

IPC: H05K3/46

CPC classification number: H05K3/4655 ,  H05K3/386 ,  H05K3/4069 ,  H05K3/4617 ,  H05K3/4626 ,  H05K3/4652 ,  H05K2201/0129 ,  H05K2201/0141 ,  H05K2201/0195 ,  H05K2201/09881 ,  H05K2203/1189 ,  Y10T428/24917

Abstract: To provide a simplified method of making a multi-layer circuit board capable of observing a high density surface mounting of electronic parts, a method is provided for making a multi-layer circuit board including a first film (A) and at least two more films, second and third films (B and C), each being made of thermoplastic polymer capable of forming an optically anisotropic melt phase. The first film (A) has a low melting point (Tm 1 ), and the second and third films (B and C) have respective melting points (Tm 2 B and Tm 2 C) higher than the melting point (Tm 1 ) of the first film (A). And at least one of the second and the third films have a circuit pattern thereon. The first to third films (A to C) are thermo compressed together with the first film (A) interposed between the second and third films (B and C). The method includes causing at least one of the circuit patterns (D) on one of the second and third films (B and C) to contact an opposing surface of the other of the second and third films (B and C) through the first film (A) during the thermo compression bonding of the first to third films (A to C).

公开(公告)号：EP1741322A1

公开(公告)日：2007-01-10

申请号：EP05716880.9

申请日：2005-03-02

Applicant: SIEMENS AKTIENGESELLSCHAFT

Inventor： BUSCH, Georg

IPC: H05K1/00 ,  H05K1/11 ,  H05K3/40 ,  H05K3/42

CPC classification number: H05K3/4626 ,  H05K1/095 ,  H05K3/0052 ,  H05K3/4602 ,  H05K3/4608 ,  H05K2201/0195 ,  H05K2201/0323 ,  H05K2201/0959 ,  H05K2201/09881 ,  H05K2203/0759 ,  H05K2203/162 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: Disclosed is a simplified, inexpensive method for producing printed circuit boards and/or corresponding constructs comprising points where through-connections are created. Such a method dispenses with the need for a very complex brushing process while using exclusively low-cost lacquer variants. Moreover, the inventive method allows additional strip conductors or appropriate layers to be guided even directly across the through-connections rather than just to said through-connections..

Abstract translation: 公开了一种用于制造印刷电路板和/或包括产生直通连接点的相应结构的简化的，便宜的方法。 这种方法无需使用非常复杂的刷涂工艺，同时仅使用低成本的漆变体。 此外，本发明的方法允许附加的条形导体或合适的层甚至直接穿过贯穿连接而不是直接引导到所述贯穿连接。