公开(公告)号：EP1121008A4

公开(公告)日：2005-02-02

申请号：EP99933214

申请日：1999-07-30

Applicant: IBIDEN CO LTD

Inventor： HIROSE NAOHIRO ,  NODA KOUTA ,  SEGAWA HIROSHI ,  EN HONJIN ,  TSUKADA KIYOTAKA ,  ISHIDA NAOTO ,  ASANO KOUJI ,  SHOUDA ATSUSHI

IPC: B23K26/38 ,  H05K1/02 ,  H05K3/00 ,  H05K3/10 ,  H05K3/28 ,  H05K3/38 ,  H05K3/42 ,  H05K3/46

CPC classification number: H05K3/4652 ,  B23K26/389 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/0201 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/0055 ,  H05K3/0094 ,  H05K3/108 ,  H05K3/28 ,  H05K3/381 ,  H05K3/383 ,  H05K3/384 ,  H05K3/427 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4661 ,  H05K2201/0195 ,  H05K2201/0352 ,  H05K2201/0358 ,  H05K2201/062 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09827 ,  H05K2201/09863 ,  H05K2201/09881 ,  H05K2203/0307 ,  H05K2203/0353 ,  H05K2203/0554 ,  H05K2203/0773 ,  H05K2203/107 ,  H05K2203/121 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: An opening is made in a resin (20) with a laser to form a viahole. A copper foil (22) etched into a thin film (3 νm) to lower the heat conductivity is used as a conformal mask, thereby making an opening (20a) in the resin (20) by fewer times of irradiation with a pulse laser beam. This prevents formation of any undercut in the resin (20) on which an interlayer resin-insulating layer is to be formed, enabling improvement in the connection reliability of the viahole.

公开(公告)号：EP0969707A3

公开(公告)日：2000-11-22

申请号：EP99201699.8

申请日：1999-05-28

Applicant: Matsushita Electric Works, Ltd.

Inventor： Yoshioka, Hirokazu ,  Yoshida, Norio ,  Tanaka, Kenichiro

IPC: H05K3/46 ,  H05K3/00

CPC classification number: H05K3/4652 ,  H05K1/116 ,  H05K3/0035 ,  H05K3/0044 ,  H05K3/0055 ,  H05K3/421 ,  H05K3/4644 ,  H05K2201/0969 ,  H05K2201/098 ,  H05K2201/09863 ,  H05K2203/025 ,  H05K2203/0554 ,  H05K2203/0796 ,  H05K2203/095 ,  H05K2203/1383 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49158 ,  Y10T29/4916 ,  Y10T29/49165

Abstract: A multilayer printed wiring board (11) is formed with a plurality of conductor layers laminated as a whole with insulating layers interposed, a non-penetrating via hole (3) provided in the insulating layer (2) as bottomed by the conductor layer (1a) exposed, a plated layer (4) provided inside the via hole (3) for electric connection between the conductor layers (1a,1b), the via hole (3) being formed to be of a concave curved surface of a radius in a range of 20 to 100 µm in axially sectioned view at continuing zone of inner periphery to bottom surface of the via hole (3), whereby the equipotential surfaces occurring upon plating the plated layer (4) are curved along the continuing zone to unify the density of current for rendering the plated layer (4) uniform in the thickness without being thinned at the continuing zone.

公开(公告)号：EP0805614A4

公开(公告)日：1998-11-25

申请号：EP96938496

申请日：1996-11-18

Applicant: TOSHIBA KK

Inventor： SASAOKA KENJI ,  ODAIRA HIROSHI ,  FUJIWARA MADOKA ,  IKEGAYA FUMITOSHI ,  MORI TAKAHIRO

IPC: H01L21/48 ,  H01L23/538 ,  H05K1/09 ,  H05K1/11 ,  H05K3/40 ,  H05K3/46 ,  H01L23/48

CPC classification number: H01L24/16 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/5383 ,  H01L23/5384 ,  H01L24/17 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/351 ,  H05K1/095 ,  H05K1/116 ,  H05K3/4069 ,  H05K3/4614 ,  H05K3/4647 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2201/09454 ,  H05K2201/0969 ,  H05K2201/09863 ,  H05K2203/1189 ,  H05K2203/1572 ,  Y10S428/901 ,  Y10T428/24917 ,  H01L2924/00

Abstract: A multilayered wiring board using conductive pillars for the interconnection of wiring layers. Since through holes are bored in the via lands of the wiring layers of the multilayered wiring board, the stress applied between the conductive pillars and wiring layers can be released at the time of connecting the conductive pillars to the via lands. Since the external side face of each conductive pillar smoothly continues to the surface of the via land at the contact section between the conductive pillar and the via land, the notch effect is relieved. Therefore, the reliability of the interconnection is secured even when a stress is applied to the connections during the manufacturing of the multilayered wiring board, and the mounting of electronic parts, etc.

公开(公告)号：EP1858308A4

公开(公告)日：2010-03-31

申请号：EP06781090

申请日：2006-07-07

Applicant: IBIDEN CO LTD

Inventor： TAKAHASHI MICHIMASA ,  MIKADO YUKINOBU ,  NAKAMURA TAKENOBU ,  AOYAMA MASAKAZU

IPC: H05K3/46

CPC classification number: H05K3/421 ,  H05K1/115 ,  H05K3/423 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/0394 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09709 ,  H05K2201/09863 ,  H05K2203/0733 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T428/31511

公开(公告)号：EP1220589B1

公开(公告)日：2008-07-30

申请号：EP01130820.2

申请日：2001-12-24

Applicant: Denso Corporation

Inventor： Yazaki, Yoshitarou ,  Yokochi, Tomohiro ,  Kondo, Koji ,  Harada, Toshikazu ,  Shiraishi, Yoshihiko

IPC: H05K3/40 ,  H05K3/46

CPC classification number: H05K3/4632 ,  H05K1/095 ,  H05K3/4069 ,  H05K3/4617 ,  H05K2201/0129 ,  H05K2201/0272 ,  H05K2201/0305 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09827 ,  H05K2201/09863 ,  H05K2203/0425 ,  H05K2203/1131 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49165 ,  Y10T428/24917

公开(公告)号：EP1121008B1

公开(公告)日：2008-07-30

申请号：EP99933214.1

申请日：1999-07-30

Applicant: IBIDEN CO., LTD.

Inventor： HIROSE, Naohiro ,  NODA, Kouta ,  SEGAWA, Hiroshi ,  EN, Honjin ,  TSUKADA, Kiyotaka ,  ISHIDA, Naoto ,  ASANO, Kouji ,  SHOUDA, Atsushi

IPC: H05K3/46

CPC classification number: H05K3/4652 ,  B23K26/389 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/0201 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/0055 ,  H05K3/0094 ,  H05K3/108 ,  H05K3/28 ,  H05K3/381 ,  H05K3/383 ,  H05K3/384 ,  H05K3/427 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4661 ,  H05K2201/0195 ,  H05K2201/0352 ,  H05K2201/0358 ,  H05K2201/062 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09827 ,  H05K2201/09863 ,  H05K2201/09881 ,  H05K2203/0307 ,  H05K2203/0353 ,  H05K2203/0554 ,  H05K2203/0773 ,  H05K2203/107 ,  H05K2203/121 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: An opening is made in a resin (20) with a laser to form a viahole. A copper foil (22) etched into a thin film (3 νm) to lower the heat conductivity is used as a conformal mask, thereby making an opening (20a) in the resin (20) by fewer times of irradiation with a pulse laser beam. This prevents formation of any undercut in the resin (20) on which an interlayer resin-insulating layer is to be formed, enabling improvement in the connection reliability of the viahole.

Abstract translation: 利用激光在树脂（20）中形成开口以形成通孔。 蚀刻成薄膜（3νm）以降低热导率的铜箔（22）用作共形掩模，由此通过用脉冲激光束照射较少次数来在树脂（20）中形成开口（20a） 。 这防止了在要形成层间树脂绝缘层的树脂20中形成任何底切，从而改善了通孔的连接可靠性。

公开(公告)号：EP1843649A3

公开(公告)日：2007-10-31

申请号：EP07013523.1

申请日：1999-07-30

Applicant: IBIDEN CO., LTD.

Inventor： Hirose , Nachiro c/o Ogaki-kita-kojou, Ibiden Kabushiki Kaisha ,  Noda, Kouta c/o Ogaki-kita-kojou,Ibiden Kabushiki Kaisha, ,  Segawa, Hiroshi c/o Ogaki-kita-kojou, Ibiden Kabushiki Kaisha, ,  En ,Honjin c/o Ogaki-kita-kojou, Ibiden Kabushiki Kaisha, ,  Tsukada, Kiyotaka c/o Gama-kojou, Ibiden Kabushiki Kaisha, ,  Ishida, Naoto c/o Gama-kojou, Ibiden Kabushiki Kaisha, ,  Asano, Kouji c/o Gama-kojou, Ibiden Kabushiki Kaisha, ,  Shouda, Atsushi c/o Gama-kojou, Ibiden Kabushiki Kaisha,

IPC: H05K3/46 ,  H05K3/38

CPC classification number: H05K3/4652 ,  B23K26/389 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/0201 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/0055 ,  H05K3/0094 ,  H05K3/108 ,  H05K3/28 ,  H05K3/381 ,  H05K3/383 ,  H05K3/384 ,  H05K3/427 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4661 ,  H05K2201/0195 ,  H05K2201/0352 ,  H05K2201/0358 ,  H05K2201/062 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09827 ,  H05K2201/09863 ,  H05K2201/09881 ,  H05K2203/0307 ,  H05K2203/0353 ,  H05K2203/0554 ,  H05K2203/0773 ,  H05K2203/107 ,  H05K2203/121 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: A method of manufacturing a multi layered printed circuit board incorporating a substrate (230) on which a lower conductive circuit (234) is formed, an insulating resin layer (250) and an upper conductive circuit (258) formed on the lower conductive circuit (234) and having a structure that the lower conductive circuit (234) and the upper conductive circuit (258) are connected to each other through a via hole (260), the method of manufacturing a multilayered printed circuit board comprising the steps of:
forming the lower conductive circuit (234) on the substrate (230); forming the insulating resin layer (250) on the lower conductive circuit; previously forming a coarsened surface (250a) on the surface of the insulating resin layer (250); forming, on the coarsened surface (250a), a metal layer (251) having an opening (251a) through which a portion of the coarsened surface (250a) is exposed; irradiating the coarsened surface (250a) exposed through the opening (251a) with a laser beam to remove the insulating resin layer to form an opening (248) for the via hole; and forming the upper conductive circuit (258) and the via hole (260).

Abstract translation: 一种多层印刷电路板，包括：形成有导电电路（334）的基板（330） 形成在导电电路（334）上的层间绝缘树脂层（350） 用于形成在所述层间绝缘树脂层（350）中形成的通孔（360）的开口（348）; 以及包括通孔（360）并形成在所述层间绝缘树脂层（350）上的另一个导电电路（358），其中，所述导电电路（334）的表面使用含有铜络合物和有机物的蚀刻溶液进行粗化处理 在用于形成通孔（360）的开口（348）的内壁上形成有酸和条状凹坑和突起。

公开(公告)号：EP1843649A2

公开(公告)日：2007-10-10

申请号：EP07013523.1

申请日：1999-07-30

Applicant: IBIDEN CO., LTD.

Inventor： Hirose , Nachiro c/o Ogaki-kita-kojou, Ibiden Kabushiki Kaisha ,  Noda, Kouta c/o Ogaki-kita-kojou,Ibiden Kabushiki Kaisha, ,  Segawa, Hiroshi c/o Ogaki-kita-kojou, Ibiden Kabushiki Kaisha, ,  En ,Honjin c/o Ogaki-kita-kojou, Ibiden Kabushiki Kaisha, ,  Tsukada, Kiyotaka c/o Gama-kojou, Ibiden Kabushiki Kaisha, ,  Ishida, Naoto c/o Gama-kojou, Ibiden Kabushiki Kaisha, ,  Asano, Kouji c/o Gama-kojou, Ibiden Kabushiki Kaisha, ,  Shouda, Atsushi c/o Gama-kojou, Ibiden Kabushiki Kaisha,

IPC: H05K3/46 ,  H05K3/38

CPC classification number: H05K3/4652 ,  B23K26/389 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/0201 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/0055 ,  H05K3/0094 ,  H05K3/108 ,  H05K3/28 ,  H05K3/381 ,  H05K3/383 ,  H05K3/384 ,  H05K3/427 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4661 ,  H05K2201/0195 ,  H05K2201/0352 ,  H05K2201/0358 ,  H05K2201/062 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09827 ,  H05K2201/09863 ,  H05K2201/09881 ,  H05K2203/0307 ,  H05K2203/0353 ,  H05K2203/0554 ,  H05K2203/0773 ,  H05K2203/107 ,  H05K2203/121 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: A method of manufacturing a multi layered printed circuit board incorporating a substrate (230) on which a lower conductive circuit (234) is formed, an insulating resin layer (250) and an upper conductive circuit (258) formed on the lower conductive circuit (234) and having a structure that the lower conductive circuit (234) and the upper conductive circuit (258) are connected to each other through a via hole (260), the method of manufacturing a multilayered printed circuit board comprising the steps of:
forming the lower conductive circuit (234) on the substrate (230); forming the insulating resin layer (250) on the lower conductive circuit; previously forming a coarsened surface (250a) on the surface of the insulating resin layer (250); forming, on the coarsened surface (250a), a metal layer (251) having an opening (251a) through which a portion of the coarsened surface (250a) is exposed; irradiating the coarsened surface (250a) exposed through the opening (251a) with a laser beam to remove the insulating resin layer to form an opening (248) for the via hole; and forming the upper conductive circuit (258) and the via hole (260).

Abstract translation: 一种制造多层印刷电路板的方法，所述多层印刷电路板结合其上形成有下导电电路（234）的基板（230），形成在下导电电路（234）上的绝缘树脂层（250）和上导电电路（258） 所述多层印刷电路板的制造方法包括以下步骤：形成下层导电电路（234）和上层导电电路（258），所述下层导电电路（234）和所述上层导电电路（258）通过通孔（260） 衬底（230）上的下导电电路（234）; 在下导电电路上形成绝缘树脂层（250）; 预先在绝缘树脂层（250）的表面上形成粗化表面（250a）; 在所述粗化表面（250a）上形成具有开口（251a）的金属层（251），所述粗化表面（250a）的一部分通过所述开口暴露; 用激光束照射通过开口（251a）暴露的粗化表面（250a）以去除绝缘树脂层以形成通孔的开口（248）; 并形成上导电电路（258）和通孔（260）。

公开(公告)号：EP1827069A3

公开(公告)日：2007-10-03

申请号：EP07075315.7

申请日：1998-01-23

Applicant: IBIDEN CO., LTD.

Inventor： Takada, Masaru, c/o Ibiden Co., Ltd. ,  Tsukada, Kiyotaka, c/o Ibiden Co., Ltd. ,  Kobayashi, Hiroyuki, c/o Ibiden Co., Ltd. ,  Minoura, Hisashi, c/o Ibiden Co., Ltd. ,  Ukai, Yoshikazu, c/o Ibiden Co., Ltd. ,  Kondo, Mitsuhiro, c/o Ibiden Co., Ltd.

IPC: H05K3/46

CPC classification number: H05K3/4652 ,  H01L21/486 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15153 ,  H01L2924/1517 ,  H05K1/0203 ,  H05K1/021 ,  H05K1/0271 ,  H05K1/0366 ,  H05K1/112 ,  H05K1/116 ,  H05K1/182 ,  H05K3/0035 ,  H05K3/0061 ,  H05K3/3468 ,  H05K3/3484 ,  H05K3/385 ,  H05K3/4038 ,  H05K3/421 ,  H05K3/423 ,  H05K3/427 ,  H05K3/428 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0305 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/0969 ,  H05K2201/09781 ,  H05K2201/09845 ,  H05K2201/09854 ,  H05K2201/09863 ,  H05K2203/0315 ,  H05K2203/041 ,  H05K2203/0554 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00014

Abstract: A method of manufacturing a printed wiring board (210) comprising at least two insulating layers (211,212,213) made of a synthetic resin, an innerlayer conductor circuit (221-225) arranged between the insulating layers, and a plurality of blind via- holes (3A-3E) formed from an outermost surface toward the innerlayer conductor circuit (221-225) and having different depths by successively irradiating a laser beam every a portion forming the blind via-hole (3A-3E), characterized in that a shallowest blind via-hole (3A-3E) is formed as a standard hole by using a standard laser beam (242) having an energy strength required for the formation of the standard hole, and the standard laser beam (242) is irradiated plural times in the formation of the blind via-holes having deeper depths (3B,3D,3E).

Abstract translation: 一种制造包括至少两个由合成树脂制成的绝缘层（211,212,213）的印刷线路板（210）的方法，布置在绝缘层之间的内层导体电路（221-225）以及多个盲通孔（ 通过在形成盲通孔（3A-3E）的每个部分上连续照射激光束而从最外表面朝向内层导体电路（221-225）形成并且具有不同深度的多个通孔（3A-3E），其特征在于， 通过使用具有形成标准孔所需的能量强度的标准激光束（242）将通孔（3A-3E）形成为标准孔，并且标准激光束（242）被多次照射 形成深度更深的盲通孔（3B，3D，3E）。

公开(公告)号：EP1816905A3

公开(公告)日：2007-10-03

申请号：EP07075316.5

申请日：1998-01-23

Applicant: IBIDEN CO., LTD.

Inventor： Takada, Masaru, c/o Ibiden Co., Ltd. ,  Tsukada, Kiyotaka, c/o Ibiden Co., Ltd. ,  Kobayashi, Hiroyuki, c/o Ibiden Co., Ltd. ,  Minoura, Hisashi, c/o Ibiden Co., Ltd. ,  Ukai, Yoshikazu, c/o Ibiden Co., Ltd. ,  Kondo, Mitsuhiro, c/o Ibiden Co., Ltd.

IPC: H05K3/46

CPC classification number: H05K3/4652 ,  H01L21/486 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15153 ,  H01L2924/1517 ,  H05K1/0203 ,  H05K1/021 ,  H05K1/0271 ,  H05K1/0366 ,  H05K1/112 ,  H05K1/116 ,  H05K1/182 ,  H05K3/0035 ,  H05K3/0061 ,  H05K3/3468 ,  H05K3/3484 ,  H05K3/385 ,  H05K3/4038 ,  H05K3/421 ,  H05K3/423 ,  H05K3/427 ,  H05K3/428 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0305 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/0969 ,  H05K2201/09781 ,  H05K2201/09845 ,  H05K2201/09854 ,  H05K2201/09863 ,  H05K2203/0315 ,  H05K2203/041 ,  H05K2203/0554 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00014

Abstract: A printed wiring board (501) comprising two or more insulating layers (516,518) on an innerlayer conductor circuit (562), a via-hole (502) extending from an outermost surface of the insulating layer (516) through the two or more insulating layers (516,518) to the innerlayer conductor circuit (562) and an inner metal plated film (521) formed in the via-hole (502) so as to electrically connect to the innerlayer conductor circuit (562) to an outer conductor circuit (561) arranged on the outermost surface, characterized in that an annular dummy land (504) for reinforcement having an opening hole (540) around the via-hole (502) is arranged in a boundary portion (517) facing the two or more insulating layers (516,518) to each other and is joined to the inner metal plated film (521).

Abstract translation: 一种印刷电路板（501），包括位于内层导体电路（562）上的两个或更多个绝缘层（516,518），从绝缘层（516）的最外表面延伸穿过两个或更多个绝缘体 （562）的层（516,518）和形成在通孔（502）中的内部金属镀膜（521），以便将内层导体电路（562）电连接到外导体电路（561） ），其特征在于，在面向所述两个或更多个绝缘层（517）的边界部分（517）中布置用于加强的具有围绕所述通孔（502）的开口孔（540）的环形虚拟焊盘（504） （516,518）彼此接合并与内侧金属镀膜（521）接合。