公开(公告)号：EP3198644A4

公开(公告)日：2018-05-23

申请号：EP14902441

申请日：2014-09-26

申请人： INTEL CORP

发明人： MEYER THORSTEN ,  JAERVINEN PAULI ,  PATTEN RICHARD

IPC分类号： H01L21/60 ,  H01L21/56 ,  H01L25/065

CPC分类号： H01L25/0657 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/481 ,  H01L23/49 ,  H01L23/528 ,  H01L24/19 ,  H01L24/20 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L24/96 ,  H01L25/07 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48235 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first encapsulation layer and a second die at least partially embedded in a second encapsulation layer. The first die may have a first plurality of die-level interconnect structures disposed at a first side of the first encapsulation layer. The IC package may also include a plurality of electrical routing features at least partially embedded in the first encapsulation layer and configured to route electrical signals between a first and second side of the first encapsulation layer. The second side may be disposed opposite to the first side. The second die may have a second plurality of die-level interconnect structures that may be electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires.

公开(公告)号：EP3198644A1

公开(公告)日：2017-08-02

申请号：EP14902441.6

申请日：2014-09-26

申请人： Intel Corporation

发明人： MEYER, Thorsten ,  JAERVINEN, Pauli ,  PATTEN, Richard

IPC分类号： H01L25/07 ,  H01L23/49

CPC分类号： H01L25/0657 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/481 ,  H01L23/49 ,  H01L23/528 ,  H01L24/19 ,  H01L24/20 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L24/96 ,  H01L25/07 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48235 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/207

摘要： Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first encapsulation layer and a second die at least partially embedded in a second encapsulation layer. The first die may have a first plurality of die-level interconnect structures disposed at a first side of the first encapsulation layer. The IC package may also include a plurality of electrical routing features at least partially embedded in the first encapsulation layer and configured to route electrical signals between a first and second side of the first encapsulation layer. The second side may be disposed opposite to the first side. The second die may have a second plurality of die-level interconnect structures that may be electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires.

摘要翻译： 本公开的实施例针对集成电路（IC）封装，其包括至少部分地嵌入在第一封装层中的第一管芯和至少部分地嵌入在第二封装层中的第二管芯。 第一管芯可具有设置在第一封装层的第一侧的第一多个管芯级互连结构。 IC封装还可以包括多个电布线特征，其至少部分地嵌入在第一封装层中并且被配置为在第一封装层的第一侧和第二侧之间布线电信号。 第二面可以与第一面相对设置。 第二管芯可以具有第二多个管芯级互连结构，其可以通过接合线与多个电布线特征的至少一个子集电耦合。

公开(公告)号：EP2779232A2

公开(公告)日：2014-09-17

申请号：EP14160005.6

申请日：2014-03-14

申请人： Renesas Electronics Corporation

发明人： Kajiwara, Ryoichi ,  Nakajo, Takuya ,  Arai, Katsuo ,  Yato, Yuichi ,  Oka, Hiroi ,  Hozoji, Hiroshi

IPC分类号： H01L23/488 ,  H01L23/49 ,  H01L21/60 ,  H01L23/31 ,  H01L23/495

CPC分类号： H01L23/49 ,  H01L21/50 ,  H01L23/293 ,  H01L23/295 ,  H01L23/3107 ,  H01L23/3192 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49562 ,  H01L23/49582 ,  H01L23/562 ,  H01L23/564 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L29/1608 ,  H01L29/2003 ,  H01L2224/0381 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/0603 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/29118 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29294 ,  H01L2224/29439 ,  H01L2224/2949 ,  H01L2224/3011 ,  H01L2224/3201 ,  H01L2224/32013 ,  H01L2224/32058 ,  H01L2224/32059 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45565 ,  H01L2224/45616 ,  H01L2224/45639 ,  H01L2224/45644 ,  H01L2224/45664 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/48724 ,  H01L2224/48739 ,  H01L2224/48744 ,  H01L2224/48755 ,  H01L2224/48824 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48855 ,  H01L2224/48997 ,  H01L2224/4903 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2224/83055 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/83439 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/8392 ,  H01L2224/83951 ,  H01L2224/85205 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/8592 ,  H01L2224/85951 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/00011 ,  H01L2924/10272 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/06 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/01013 ,  H01L2924/01051 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/83205

摘要： A semiconductor device (20, 24, 29, 32, 35, 38) includes a die pad (6), a wide gap semiconductor chip (SiC or GaN) (1) mounted on the die pad (6), a porous first sintered Ag layer (16) bonding the die pad (6) and the chip (1), and a reinforcing resin portion (17) covering a surface of the first sintered Ag layer (16) and a part of a side surface of the chip (1) and formed in a fillet shape. The semiconductor device (20, 24, 29, 32, 35, 38) further includes electrodes (1g, 1h, 2, 3, 4) on its main (1a) and back (1b) surfaces, the electrodes (1g, 1h, 2, 3, 4) being electrically connected to leads (7, 9, 11, 39), wherein the electrical connection at the front side is a wire (18, 19, 25, 26) connection and the electrical connection at the back side is the first sintered Ag layer (16). A porous second sintered Ag layer (36) or a second resin portion (30) reinforces the wire bonding portion on the electrode (1g, 2, 3). The semiconductor device (20, 24, 29, 32, 35, 38) further includes a sealing body (third resin) (14) which covers the chip (1), the first sintered Ag layer (16), and a part of the die pad (6).

摘要翻译： 一种半导体器件（20，24，29，32，35，38）包括一个垫（6），一个宽带隙半导体芯片（SiC或GaN）的安装在所述管芯焊盘（6）（1），多孔第一烧结 Ag层（16）粘合在管芯焊盘（6）和所述芯片（1），和一个增强树脂部（17），其覆盖所述第一烧结Ag层（16）的表面和芯片的侧表面的一部分（ 1）和形成为圆角形状。 的半导体器件（20，24，29，32，35，38）还包括电极（1G，1H，2，3，4）在其主（1a）和背面（1b）中的表面，所述电极（1G，1H， 2，3，4）被电连接到引线（7，9，11，39），其中，在所述前侧的电连接是电线（18，19，25，26）连接，并且在所述背面上的电连接 是第一烧结Ag层（16）。 多孔烧结第二Ag层（36）或第二树脂部分（30）迫使纯粹在电极上的引线键合部分（1克，2，3）。 的半导体器件（20，24，29，32，35，38）还包括一个密封体（第三树脂）（14），其覆盖所述芯片（1），所述第一烧结Ag层（16），和的一个部分 垫（6）。