公开(公告)号：EP1827068A2

公开(公告)日：2007-08-29

申请号：EP07075317.3

申请日：1998-01-23

Applicant: IBIDEN CO., LTD.

Inventor： Takada, Masaru c/o Ibiden Co., Ltd. ,  Tsukada, Kiyotaka c/o Ibiden Co., Ltd. ,  Kobayashi, Hiroyuki c/o Ibiden Co., Ltd. ,  Minoura, Hisashi c/o Ibiden Co., Ltd. ,  Ukai, Yoshikazu c/o Ibiden Co., Ltd. ,  Kondo, Mitsuhiro c/o Ibiden Co., Ltd.

IPC: H05K3/40 ,  H05K3/46

CPC classification number: H05K3/4652 ,  H01L21/486 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15153 ,  H01L2924/1517 ,  H05K1/0203 ,  H05K1/021 ,  H05K1/0271 ,  H05K1/0366 ,  H05K1/112 ,  H05K1/116 ,  H05K1/182 ,  H05K3/0035 ,  H05K3/0061 ,  H05K3/3468 ,  H05K3/3484 ,  H05K3/385 ,  H05K3/4038 ,  H05K3/421 ,  H05K3/423 ,  H05K3/427 ,  H05K3/428 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0305 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/0969 ,  H05K2201/09781 ,  H05K2201/09845 ,  H05K2201/09854 ,  H05K2201/09863 ,  H05K2203/0315 ,  H05K2203/041 ,  H05K2203/0554 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00014

Abstract: A printed wiring board (802) comprising an insulating substrate (806), a conductor pattern formed on a surface of the insulating substrate (806), a solder filling hole (801) passing through the insulating substrate (806) and arriving at an upper surface of the conductor pattern (851) and a solder (807) filled in the solder filling hole (801), characterized in that the insulating substrate (806) includes fibers (861) therein, and end portions (863) of the fibers (861) protrude from a wall face (810) of the solder filling hole (801) and encroach into the solder (807).

Abstract translation: 一种印刷电路板（802），包括绝缘基板（806），形成在所述绝缘基板（806）的表面上的导体图案，穿过所述绝缘基板（806）并到达所述绝缘基板 导体图案（851）的表面和填充在焊料填充孔（801）中的焊料（807），其特征在于，绝缘基板（806）包括纤维（861），纤维的端部（863） 861）从焊料填充孔（801）的壁面（810）突出并侵入焊料（807）。

公开(公告)号：EP1494516A3

公开(公告)日：2007-04-04

申请号：EP04253645.8

申请日：2004-06-17

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Muramatsu, Shigetsugu ,  Hizume, Tohru

IPC: H05K3/46

CPC classification number: H05K3/4644 ,  H05K3/005 ,  H05K3/421 ,  H05K2201/0969 ,  H05K2201/09827 ,  H05K2201/09863 ,  H05K2203/0108 ,  H05K2203/1189

Abstract: A wiring board is disclosed that includes a first insulating layer (110), a conductor (155,160,170) which is formed on a surface of the first insulating layer (110), and a second insulating layer (180) which is formed on surfaces of the first insulating layer (110) and of the conductor (155,160,170). The wiring board is provided with a semispherical-shaped or conical-shaped hole-forming portion (200) which penetrates through the second insulating layer (180) into the conductor (155,160,170).

公开(公告)号：EP1494516A2

公开(公告)日：2005-01-05

申请号：EP04253645.8

申请日：2004-06-17

Applicant: Shinko Electric Industries Co., Ltd.

Inventor： Muramatsu, Shigetsugu ,  Hizume, Tohru

IPC: H05K3/46

CPC classification number: H05K3/4644 ,  H05K3/005 ,  H05K3/421 ,  H05K2201/0969 ,  H05K2201/09827 ,  H05K2201/09863 ,  H05K2203/0108 ,  H05K2203/1189

Abstract: A wiring board is disclosed that includes a first insulating layer (110), a conductor (155,160,170) which is formed on a surface of the first insulating layer (110), and a second insulating layer (180) which is formed on surfaces of the first insulating layer (110) and of the conductor (155,160,170). The wiring board is provided with a semispherical-shaped or conical-shaped hole-forming portion (200) which penetrates through the second insulating layer (180) into the conductor (155,160,170).

Abstract translation: 公开了一种布线板，其包括第一绝缘层（110），形成在第一绝缘层（110）的表面上的导体（155,160,170）以及形成在第一绝缘层（110）的表面上的第二绝缘层（180） 第一绝缘层（110）和导体（155,160,170）。 布线板设置有穿过第二绝缘层（180）进入导体（155,160,170）的半球形或圆锥形的孔形成部分（200）。

公开(公告)号：EP1220589A2

公开(公告)日：2002-07-03

申请号：EP01130820.2

申请日：2001-12-24

Applicant: Denso Corporation

Inventor： Yazaki, Yoshitarou ,  Yokochi, Tomohiro ,  Kondo, Koji ,  Harada, Toshikazu ,  Shiraishi, Yoshihiko

IPC: H05K3/40 ,  H05K3/46

CPC classification number: H05K3/4632 ,  H05K1/095 ,  H05K3/4069 ,  H05K3/4617 ,  H05K2201/0129 ,  H05K2201/0272 ,  H05K2201/0305 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09827 ,  H05K2201/09863 ,  H05K2203/0425 ,  H05K2203/1131 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49165 ,  Y10T428/24917

Abstract: Conductive paste (50) containing tin particles (61) and silver particles (62) is packed in a substantially cylindrical via hole (24) formed in a thermoplastic resin film (23) that interposes between conductor patterns (22) and is hot-pressed from both sides. When the metal particles contained in the conductive paste (50) are sintered to form a unified conductive compound (51), the volume of the conductive paste (50) shrinks. Synchronously, the resin film (23) around the via-hole (24) protrudes into the via-hole (24). Therefore, the shape of the side wall on the cross-section of the conductive compound (51) provides an arch shape, and a side wall (51a) adjacent to a junction part (51b) of the conductive compound (51), which contacts the conductor pattern (22), is formed with an inclination. Therefore, it is possible to prevent the stress concentration due to deformation of the board.

公开(公告)号：EP1121008A1

公开(公告)日：2001-08-01

申请号：EP99933214.1

申请日：1999-07-30

Applicant: IBIDEN CO., LTD.

Inventor： HIROSE, Naohiro ,  NODA, Kouta ,  SEGAWA, Hiroshi ,  EN, Honjin ,  TSUKADA, Kiyotaka ,  ISHIDA, Naoto ,  ASANO, Kouji ,  SHOUDA, Atsushi

IPC: H05K3/46

CPC classification number: H05K3/4652 ,  B23K26/389 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/0201 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/0055 ,  H05K3/0094 ,  H05K3/108 ,  H05K3/28 ,  H05K3/381 ,  H05K3/383 ,  H05K3/384 ,  H05K3/427 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4661 ,  H05K2201/0195 ,  H05K2201/0352 ,  H05K2201/0358 ,  H05K2201/062 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09827 ,  H05K2201/09863 ,  H05K2201/09881 ,  H05K2203/0307 ,  H05K2203/0353 ,  H05K2203/0554 ,  H05K2203/0773 ,  H05K2203/107 ,  H05K2203/121 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: An opening is formed in resin 20 by a laser beam so that a via hole is formed. At this time, copper foil 22, the thickness of which is reduced (to 3 µ m) by performing etching to lower the thermal conductivity is used as a conformal mask. Therefore, an opening 20a can be formed in the resin 20 if the number of irradiation of pulse-shape laser beam is reduced. Therefore, occurrence of undercut of the resin 20 which forms an interlayer insulating resin layer can be prevented. Thus, the reliability of the connection of the via holes can be improved.

Abstract translation: 通过激光束在树脂20中形成开口，从而形成通孔。 此时，通过执行蚀刻以降低热导率来减小厚度（至3μm）的铜箔22被用作共形掩模。 因此，如果减少脉冲形状激光束的照射次数，则可以在树脂20中形成开口20a。 因此，可以防止形成层间绝缘树脂层的树脂20发生底切。 因此，可以提高通孔连接的可靠性。

公开(公告)号：EP0971570A1

公开(公告)日：2000-01-12

申请号：EP98901002.0

申请日：1998-01-23

Applicant: IBIDEN CO., LTD.

Inventor： TAKADA, Masaru, Ibiden Co., Ltd. ,  TSUKADA, Kiyotaka, Ibiden Co., Ltd. ,  KOBAYASHI, Hiroyuki ,  MINOURA, Hisashi ,  UKAI, Yoshikazu ,  KONDO, Mitsuhiro

IPC: H05K3/46

CPC classification number: H05K3/4652 ,  H01L21/486 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15153 ,  H01L2924/1517 ,  H05K1/0203 ,  H05K1/021 ,  H05K1/0271 ,  H05K1/0366 ,  H05K1/112 ,  H05K1/116 ,  H05K1/182 ,  H05K3/0035 ,  H05K3/0061 ,  H05K3/3468 ,  H05K3/3484 ,  H05K3/385 ,  H05K3/4038 ,  H05K3/421 ,  H05K3/423 ,  H05K3/427 ,  H05K3/428 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0305 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/0969 ,  H05K2201/09781 ,  H05K2201/09845 ,  H05K2201/09854 ,  H05K2201/09863 ,  H05K2203/0315 ,  H05K2203/041 ,  H05K2203/0554 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00014

Abstract: In the production of a printed wiring board comprising innerlayer conductor circuits 161, 131 arranged among insulating layers 101∼103 and blind via-holes 141, 142 formed from an outermost surface of the insulating layer toward the innerlayer conductor circuit, an opening hole 160 is previously formed in a central portion of the innerlayer conductor circuit 161 located at the bottom of the blind via-hole 141, and laser beams are irradiated from the outermost surface of the insulating layer to form the blind via-holes 141, 142. Thereafter, a metal plated film is formed on surfaces of the innerlayer conductor circuits 13, 161 and the blind via-holes 141, 142.

Abstract translation: 在制造包括布置在绝缘层101〜103之间的内层导体电路161,131和从绝缘层的最外表面朝向内层导体电路形成的盲通孔141,142的印刷线路板时，开孔160是 预先形成在位于盲通孔141底部的内层导体电路161的中心部分，并且从绝缘层的最外表面照射激光束以形成盲通孔141,142。之后， 在内层导体电路13,161和盲通孔141,142的表面上形成金属镀膜。

公开(公告)号：EP2988883A1

公开(公告)日：2016-03-02

申请号：EP14756616.0

申请日：2014-02-27

Applicant: Texas Instruments Incorporated

Inventor： JOHNSON, Peter, B. ,  WYGANT, Ira, Oaktree

IPC: B06B1/02

CPC classification number: B06B1/0292 ,  B06B2201/76 ,  B81B7/007 ,  B81B2203/0127 ,  B81B2207/096 ,  B81C1/00301 ,  B81C2201/013 ,  B81C2203/036 ,  H02N1/006 ,  H04R19/005 ,  H05K2201/09845 ,  H05K2201/09863

Abstract: A Capacitive Micromachined Ultrasonic Transducer (CMUT) device includes at least one CMUT cell including a first substrate of a single crystal material having a top side including a patterned dielectric layer thereon including a thick and a thin dielectric region, and a through-substrate via (TSV) extending a full thickness of the first substrate. The TSV is formed of the single crystal material, is electrically isolated by isolation regions in the single crystal material, and is positioned under a top side contact area of the first substrate. A membrane layer is bonded to the thick dielectric region and over the thin dielectric region to provide a movable membrane over a micro-electro-mechanical system (MEMS) cavity. A metal layer is over the top side substrate contact area and over the movable membrane including coupling of the top side substrate contact area to the movable membrane.

Abstract translation: 电容式微加工超声波传感器（CMUT）装置包括至少一个CMUT单元，其包括单晶材料的第一基板，其具有包括厚和薄的电介质区域的在其上的图案化电介质层的顶侧，以及贯穿基板通孔 TSV）延伸第一基板的整个厚度。 TSV由单晶材料形成，通过单晶材料中的隔离区电隔离，并且位于第一基板的顶侧接触区域的下方。 膜层结合到厚电介质区域和薄介电区域上，以在微机电系统（MEMS）空腔上提供可移动膜。 金属层在顶侧基板接触区域之上并且在可移动膜上方，包括顶侧基板接触区域与可动膜的耦合。

公开(公告)号：EP2981158A1

公开(公告)日：2016-02-03

申请号：EP14774851.1

申请日：2014-03-26

Applicant: Kyocera Corporation

Inventor： KAJITA, Satoshi ,  HAGIHARA, Mitsuhiro ,  MATSUMOTO, Yuuhei

IPC: H05K3/46 ,  H05K1/11

CPC classification number: H05K1/0306 ,  H05K1/0298 ,  H05K1/036 ,  H05K1/09 ,  H05K1/115 ,  H05K1/181 ,  H05K3/0038 ,  H05K3/421 ,  H05K3/4602 ,  H05K3/4655 ,  H05K2201/0116 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/0266 ,  H05K2201/09845 ,  H05K2201/09854 ,  H05K2201/09863 ,  H05K2201/2072

Abstract: A wiring board (3) in accordance with an embodiment of the invention includes: an inorganic insulating layer (13) having a via hole (V) formed so as to penetrate the inorganic insulating layer (13) in a thickness direction thereof; a conductive layer (11) disposed on the inorganic insulating layer (13); and a via conductor (12) which adheres to an inner wall (W) of the via hole (V) and is connected with the conductive layer (11). The inorganic insulating layer (13) includes a first section (33) including a plurality of inorganic insulating particles (16) partly connected to each other, and a resin portion (18) located in gaps (17) between the inorganic insulating particles (16), and a second section (34) which is interposed between the first section (33) and the via conductor (12), including a plurality of inorganic insulating particles (16) partly connected to each other, and a conducting portion (19) composed of part of the via conductor (12) which is located in gaps (17) between the inorganic insulating particles (16).

Abstract translation: 本发明的一个实施方式的布线基板（3）具备：无机绝缘层（13），其具有在厚度方向贯通无机绝缘层（13）的通路孔（V） 设置在所述无机绝缘层（13）上的导电层（11）; 和通孔导体（12），其粘附到通孔（V）的内壁（W）并与导电层（11）连接。 无机绝缘层（13）包括：包含部分彼此连接的多个无机绝缘粒子（16）的第一部分（33）和位于无机绝缘粒子（16）之间的间隙（17）中的树脂部分（18） ）以及介于第一部分（33）和通孔导体（12）之间的包括部分彼此连接的多个无机绝缘粒子（16）的第二部分（34）以及导电部分（19） 由位于无机绝缘粒子（16）之间的间隙（17）中的部分过孔导体（12）构成。

公开(公告)号：EP1019986B1

公开(公告)日：2008-06-18

申请号：EP98952161.2

申请日：1998-10-07

Applicant: Dimensional Circuits Corp.

Inventor： GREGOIRE, George, D.

IPC: H05K3/46 ,  H05K3/00 ,  H01R12/32

CPC classification number: H05K3/005 ,  H05K1/095 ,  H05K1/112 ,  H05K1/115 ,  H05K3/0014 ,  H05K3/061 ,  H05K3/107 ,  H05K3/1241 ,  H05K3/4069 ,  H05K3/4614 ,  H05K3/4617 ,  H05K3/465 ,  H05K3/4652 ,  H05K2201/0394 ,  H05K2201/09036 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09863 ,  H05K2201/09981 ,  H05K2203/0108 ,  H05K2203/025 ,  H05K2203/041 ,  H05K2203/0746 ,  H05K2203/095 ,  H05K2203/1189 ,  H05K2203/1572 ,  Y10T29/49126 ,  Y10T29/49158 ,  Y10T29/49165 ,  Y10T29/49167

Abstract: A wiring board construction (10) includes at least one microvia (12) disposed in a base substrate (14) and includes a deep imprinted cup shaped in the top surface thereof (24). A conductor material is disposed within the recess (26), and has a portion disposed at the bottom thereof. A conductor disposed at a bottom surface of the substrate opposite to the conductor material bottom portion (31) helps to complete an electrically conductive path through the substrate.

公开(公告)号：EP1858308A1

公开(公告)日：2007-11-21

申请号：EP06781090.3

申请日：2006-07-07

Applicant: IBIDEN CO., LTD.

Inventor： TAKAHASHI, Michimasa, c/o IBIDEN CO., LTD. ,  MIKADO, Yukinobu, c/o IBIDEN CO., LTD. ,  NAKAMURA, Takenobu, c/o IBIDEN CO., LTD. ,  AOYAMA, Masakazu, c/o IBIDEN CO., LTD.

IPC: H05K3/46

CPC classification number: H05K3/421 ,  H05K1/115 ,  H05K3/423 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/0394 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09709 ,  H05K2201/09863 ,  H05K2203/0733 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T428/31511

Abstract: There is provided a multilayer printed wiring board in which insulating layers and conductor layers are stacked alternately on each other and the conductor layers are electrically connected to each other through viaholes formed in the insulating layers. Each of the viaholes has at least a part thereof formed to bulge in a direction generally orthogonal to the direction of thickness of the insulating layer. This structure enables controlling such external stress as drop shock generated when the board is dropped and preventing the insulating substrate from warping, which leads to preventing cracking and disconnection of conductor circuit and minimizes the decrease of reliability and resistance to drop shock of the mounting board.

Abstract translation: 提供了一种多层印刷线路板，其中绝缘层和导体层彼此交替堆叠并且导体层通过形成在绝缘层中的通孔彼此电连接。 每个通孔的至少一部分形成为在大致垂直于绝缘层的厚度方向的方向上凸出。 这种结构能够控制这样的外部应力，例如当电路板掉落时产生的跌落冲击，并且防止绝缘基板翘曲，这导致防止导体电路的开裂和断开，并且使安装板的可靠性和抗跌落冲击性的降低最小化。