公开(公告)号：EP1855516A1

公开(公告)日：2007-11-14

申请号：EP06715221.5

申请日：2006-03-03

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： KAWAKAMI, Hiromichi ,  FUJITA, Iwao ,  TOSE, Makoto ,  SAITO, Yoshifumi ,  KIMURA, Masahiro

IPC: H05K3/28 ,  H01L23/12 ,  H05K3/46

CPC classification number: H01L24/81 ,  H01L21/4807 ,  H01L21/481 ,  H01L23/15 ,  H01L23/24 ,  H01L23/3135 ,  H01L23/315 ,  H01L23/3185 ,  H01L23/49894 ,  H01L24/48 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/81011 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/8121 ,  H01L2224/81355 ,  H01L2224/81395 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15174 ,  H01L2924/181 ,  H01L2924/19105 ,  H05K1/0306 ,  H05K3/282 ,  H05K3/284 ,  H05K2201/0162 ,  H05K2201/0179 ,  H05K2203/1316 ,  H05K2203/1322 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A ceramic multilayer substrate which has excellent migration resistance and high bonding strength between a resin sealing material and a ceramic multilayer substrate body, and its manufacturing method are obtained.
The entire laminated substrate body (2) including lands (16) and (17), and external electrodes (24) and (25) is covered with a siloxane film formed by means of a PVD process. The thickness of the siloxane film is set less than 100 nm. After that, external electrodes (16) and (17) of a mounting component (11) are electrically connected and firmly hold to the lands (16) and (17) of the laminated substrate body 2 via solder (19). Next, a resin sealing material (4) for sealing the mounting component (11) is formed on the laminated substrate body (2).

Abstract translation: 获得树脂密封材料和陶瓷多层基板主体之间具有优异的耐迁移性和高粘结强度的陶瓷多层基板及其制造方法。 包括焊盘（16）和（17）以及外部电极（24）和（25）的整个层叠基板主体（2）被通过PVD工艺形成的硅氧烷膜覆盖。 硅氧烷膜的厚度设定为小于100nm。 之后，安装部件（11）的外部电极（16）和（17）通过焊料（19）电连接并牢固地保持在叠层基板主体2的焊盘（16）和（17）上。 接着，在层叠基板主体（2）上形成用于密封安装部件（11）的树脂密封材料（4）。

公开(公告)号：EP1589798A1

公开(公告)日：2005-10-26

申请号：EP03815594.1

申请日：2003-01-31

Applicant: FUJITSU LIMITED

Inventor： KOYAMA, Hideki c/o FUJITSU LIMITED

IPC: H05K3/46 ,  H01L23/12 ,  H01P3/08

CPC classification number: H01L23/49822 ,  H01L23/50 ,  H01L2224/16 ,  H01L2924/09701 ,  H01L2924/3011 ,  H01P3/088 ,  H05K1/0298 ,  H05K1/112 ,  H05K1/115 ,  H05K1/162 ,  H05K3/429 ,  H05K3/4641 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/10674

Abstract: A multilayer printed board comprising a plurality of capacitive coupling layers (6) each consisting of a dielectric layer (4) and a power supply layer (3) and a ground layer (5) facing each other while sandwiching the dielectric layer (4), first vias (7) connecting between the power supply layers (3) included in the plurality of capacitive coupling layers (6), and second vias (8) connecting between the ground layers (5) included in the plurality of capacitive coupling layers (6).

Abstract translation: 一种多层印刷电路板，包括多个电容耦合层（6），每个电容耦合层由电介质层（4）和电源层（3）和接地层（5）构成，同时夹着电介质层（4）， 连接在多个电容耦合层（6）中的电源层（3）之间的第一通孔（7）和连接在多个电容耦合层（6）中包括的接地层（5）之间的第二通孔（8） ）。

公开(公告)号：EP1551037A1

公开(公告)日：2005-07-06

申请号：EP04405004.5

申请日：2004-01-05

Applicant: Alcan Technology & Management Ltd.

Inventor： Ziegler, Andreas ,  Dörr, Norman ,  Hammon, Werner ,  Lüthi, Markus ,  Lohwasse, Wolfgang ,  Reinhold, Matthias

IPC: H01B7/08 ,  H05K3/20 ,  H05K3/46

CPC classification number: H05K3/245 ,  H01B7/0861 ,  H05K1/0393 ,  H05K3/12 ,  H05K3/207 ,  H05K3/281 ,  H05K3/4611 ,  H05K3/4635 ,  H05K2201/0179 ,  H05K2201/0715 ,  H05K2201/098 ,  H05K2203/0113 ,  H05K2203/1476

Abstract: Bei einem flexiblen Träger (10) mit einer Basisschicht (12) aus Kunststoff und wenigstens einer mit elektrisch leitfähiger Farbe zumindest auf der Basisschicht (12) einseitig aufgedruckten, elektrisch leitfähigen Struktur (20) ist die wenigstens eine elektrisch leitfähige Struktur (20) zwischen der Basisschicht (12) und wenigstens einer Deckschicht (14) aus Kunststoff und jede der gegebenenfalls weiteren elektrisch leitfähigen Strukturen (22) zwischen jeweils zwei aufeinander der folgenden weiteren Deckschichten angeordnet, und die Basisschicht (12) ist mit der wenigsten einen Deckschicht (14) und jede der gegebenenfalls weiteren Deckschichten ist mit den angrenzenden Deckschichten verbunden.

Abstract translation: 具有导电结构的柔性载体（10）作为电路，具有使用导电油墨的电路在至少一侧印刷的塑料基层（12）。 所述印刷电路位于所述基底层与至少一个塑料覆盖层（14）之间，所述至少一个塑料覆盖层（14）在一侧具有另外的印刷电路（22）。 该结构与中间层（18）一起被外部阻挡层（16）覆盖，全部粘合在一起。

公开(公告)号：EP1444710A1

公开(公告)日：2004-08-11

申请号：EP02778712.6

申请日：2002-11-01

Applicant: H.C. Starck Inc.

Inventor： KUMAR, Prabhat ,  UHLENHUT, Henning

IPC: H01G4/10

CPC classification number: H01G9/15 ,  H01G4/10 ,  H01G11/48 ,  H05K1/162 ,  H05K2201/0179 ,  H05K2201/0329 ,  H05K2201/09763 ,  Y02E60/13

Abstract: The invention relates to a thin film capacitor containing (a) a substrate, (b) a first polymeric film comprising an electrically conductive polymer located on the substrate, (c) a pentoxide layer selected from the group consisting of tantalum pentoxide, or niobium pentoxide, and mixtures thereof, (d) a second polymeric film comprising an electrically conductive polymer located on the pentoxide layer.

公开(公告)号：EP1251530A2

公开(公告)日：2002-10-23

申请号：EP02252632.1

申请日：2002-04-15

Applicant: Shipley Company LLC

Inventor： Knudsen, Philip D. ,  Allen, Craig S.

IPC: H01G4/30

CPC classification number: H01G4/206 ,  H05K1/162 ,  H05K2201/0129 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0195 ,  H05K2201/0323 ,  H05K2201/09309 ,  Y10T428/24975 ,  Y10T428/30

Abstract: A dielectric composed of a core material between two polymer layers that have permittivity values less than the core material. The polymer layers provide structural integrity for the dielectric. The dielectric can be employed in a capacitor to fine tune the capacitance of the capacitor. The dielectric and the capacitor may have a thickness in the micron range.
Accordingly, the dielectric and capacitor provide for the miniaturization of electronic devices.
The dielectric may be employed in decoupling capacitors to reduce noise in electronic devices.

公开(公告)号：EP1018291B1

公开(公告)日：2002-10-02

申请号：EP98937029.1

申请日：1998-07-20

Applicant: MINNESOTA MINING AND MANUFACTURING COMPANY

Inventor： YANG, Rui ,  TRUONG, Thach, G. ,  MOONEY, Justine, A. ,  DAVID, Moses, M.

IPC: H05K3/28 ,  H05K3/38

CPC classification number: H01L23/4985 ,  H01L23/5387 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0393 ,  H05K3/28 ,  H05K3/388 ,  H05K2201/0179 ,  H05K2201/0323 ,  Y10T428/24917 ,  Y10T428/30 ,  Y10T428/31681 ,  H01L2924/00

Abstract: A flexible circuit carrier (1) including at least one layer of polymer dielectric material (2), at least one layer of conductive material (3) thereover, each layer having two major surfaces, at least one of said layers having at least one aperture therein, wherein at least one layer has a material (4) coated on at least a portion thereof having a Young's Modulus of from 100 to 200 GPa, a dielectric constant (between 45 MHz and 20 GHz) of from 8 to 12, and a Vickers hardness of from 2000 to 9000 kg/mm2 namely diamond-like carbon.

公开(公告)号：EP1170797A2

公开(公告)日：2002-01-09

申请号：EP01305412.7

申请日：2001-06-22

Applicant: ALPS ELECTRIC CO., LTD.

Inventor： Murata, Shinji, c/o Alps Electric Co. Ltd. ,  Yamamura, Ken, c/o Alps Electric Co. Ltd ,  Tokuta, Mitsuru, c/o Alps Electric Co. Ltd

IPC: H01L25/16 ,  H01G4/06

CPC classification number: H01L28/40 ,  H01L2224/4813 ,  H01L2924/19107 ,  H05K1/0306 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/0023 ,  H05K3/108 ,  H05K3/386 ,  H05K3/388 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/09763 ,  H05K2201/09909

Abstract: In order to provide an electronic circuit board capable of preventing the breakdown voltage of a capacitor element from dropping and excellent in high frequency performance, a positive type photoresist is spin-coated over the surface of an alumina substrate (1) and is exposed to light and developed to form an insulating layer (5), partially followed by formation of a capacitor element by successively stacking a lower electrode, a dielectric layer (3) and an upper electrode (4) over this insulating layer, further followed by formation of a resistance element (13), an inductor element (14) and a transmission line (15), each in a filmy state, over the surface of the alumina substrate.

公开(公告)号：EP1139353A2

公开(公告)日：2001-10-04

申请号：EP01301805.6

申请日：2001-02-28

Applicant: VICTOR COMPANY OF JAPAN, LTD.

Inventor： Shindoh, Motoshi ,  Segawa, Keiji ,  Otsuki, Mitsuru

IPC: H01C7/18

CPC classification number: H05K1/167 ,  H01C17/12 ,  H05K1/0206 ,  H05K1/165 ,  H05K3/388 ,  H05K3/4644 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0187 ,  H05K2201/0209 ,  H05K2201/0317 ,  H05K2201/09509 ,  H05K2201/09763 ,  H05K2203/0361 ,  Y10T29/49082

Abstract: The invention provides a production method capable of forming a thin film resistance element having a thickness and a shape controlled in a high accuracy in a printed circuit board (core material). The production method of a thin film resistance element formed on a printed circuit board, has the steps of forming a thin film resistance layer having a predetermined thickness on the printed circuit board through an insulation layer by a dry process used in producing a semiconductor, forming an electrically conductive layer on the thin resistance layer, and etching the electrically conductive layer selectively so as to make, at least, a pair of electrically conductive pads, resulting in the thin film resistance element having a predetermined value of resistivity between the pair of electrically conductive pads. Thereby, it is possible to form the thin film resistance element having a thickness and a shape controlled in a high accuracy on the printed circuit board (core material).

Abstract translation: 本发明提供一种能够形成具有一定厚度和在印刷电路板（芯材）的高精确度控制的形状的薄膜电阻元件的制造方法。 形成在印刷电路板的薄膜电阻元件的制造方法，具有形成在制造半导体使用的干法具有通过向绝缘层上的印刷电路板的预定厚度的薄膜电阻层的工序，形成 薄电阻层上的导电层，并且选择性地蚀刻导电层，以使至少一对导电焊盘，在薄膜电阻元件所得到的具有一对电之间的电阻率的预定值 导电衬垫。 由此，可以形成具有厚度和在高精度地控制在印刷电路板（芯材）的形状的薄膜电阻元件。

公开(公告)号：EP1096838A2

公开(公告)日：2001-05-02

申请号：EP00309340.8

申请日：2000-10-24

Applicant: Microcoating Technologies

Inventor： Hunt, Andrew T. ,  Lin, Wen-Yi ,  Carpenter, Richard W.

IPC: H05K1/16

CPC classification number: H05K1/162 ,  H05K1/167 ,  H05K3/4623 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2203/0338 ,  H05K2203/1338 ,  Y10T428/24917

Abstract: Nanolaminates are formed by alternating deposition, e.g., by combustion chemical vapor deposition (CCVD), layers of resistive material and layers of dielectric material. Outer resistive material layers are patterned to form discrete patches of resistive material. Electrical pathways between opposed patches of resistive material on opposite sides of the laminate act as capacitors. Electrical pathways horizontally through resistive material layers, which may be connected by via plated holes, act as resistors.

公开(公告)号：EP0713358A3

公开(公告)日：1997-11-05

申请号：EP95308110.6

申请日：1995-11-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Frankeny, Jerome Albert ,  Frankeny, Richard Francis ,  Hayden, Terry Frederick ,  Imken, Ronald Lann ,  Rice, Janet Louise ,  Vanderlee, Keith Allan

IPC: H05K1/16 ,  H05K3/46

CPC classification number: H05K3/462 ,  H05K1/162 ,  H05K3/0023 ,  H05K3/0094 ,  H05K3/4623 ,  H05K3/4641 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2201/10378 ,  H05K2203/0307

Abstract: A fine pitch pattern multilayer printed circuit board has laminar stackable board layers providing power distribution, signal distribution and capacitive decoupling. The board layers may be fabricated by beginning with a metallic core 1, patterning the core, selectively enclosing the core in a dielectric 6, selectively depositing metal 12 to form vias 13, plugs 14 and signal lines 16, and forming dendrites 19 with joining metallurgy on the vias and plugs to provide stackable connections from above or below the plane of the board layer. In addition, a sol-gel process may be used to form a thin high dielectric constant crystalline film 27 onto a metallic sheet 26 followed with a deposition of a metallic layer 29 onto the high dielectric constant film. The film serves as the dielectric of a capacitor layer which is thereafter in succession patterned, covered by a dielectric 40, and has selectively deposited a metallic layer 42 for interconnecting the capacitor and forming vias 37, 38. The ends of the vias are thereafter subject to dendritic growth and joining metallurgy to provide stackable interconnection capability. A multilayer composite laminar stackable circuit board structure is created using, as appropriate, layers having metallic cores and layers having capacitively configured cores. The multilayer laminar stackable circuit board provides direct vertical connection between surface mounted electronic components and the power, signal and capacitive decoupling layers of the composite board through the dendrites and joining metallurgy of the via and plug formations.