公开(公告)号：EP2584690A4

公开(公告)日：2018-02-28

申请号：EP11798125

申请日：2011-06-21

申请人： HITACHI AUTOMOTIVE SYSTEMS LTD

发明人： SHINOHARA SHUICHI ,  NAKAJIMA KENICHIRO ,  SASAKI KANAME

IPC分类号： H02M7/48 ,  H05K7/20

CPC分类号： H02M7/537 ,  H01L23/473 ,  H01L24/36 ,  H01L24/40 ,  H01L25/072 ,  H01L2224/40137 ,  H01L2224/8384 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H02M7/003 ,  H02M2001/327 ,  H05K7/20927 ,  H01L2924/00012 ,  H01L2924/00

摘要： A power converter device includes first, second, and third semiconductor modules respectively provided for three phases of a 3 phase inverter circuit, and incorporating upper and lower arms series circuit, and a flow path forming cabinet in a rectangular prism shape having an electric equipment containing space and a coolant flow path formed to surround the electric equipment containing space, the coolant flow path includes a first flow path provided along a first side face of the flow path forming cabinet, a second flow path provided along a second side face contiguous to one side of the first side face and connected to one end of the first flow path, and a third flow path provided along a third side face contiguous to other side of the first side face and connected to other end of the first flow path, the first semiconductor module is arranged at the first flow path in parallel with the first side face, the second semiconductor module is arranged at the second flow path in parallel with the second side face, and the third semiconductor module is arranged at the third flow path in parallel with the third side face.

公开(公告)号：EP2555408A4

公开(公告)日：2018-01-24

申请号：EP11765681

申请日：2011-03-30

申请人： HITACHI AUTOMOTIVE SYSTEMS LTD

发明人： MAEDA KEN ,  NAKAJIMA KENICHIRO ,  KASE MASAMICHI

IPC分类号： H02M7/48

CPC分类号： H05K7/2089 ,  B60L11/123 ,  B60L11/14 ,  B60L2210/40 ,  H01L24/36 ,  H01L24/40 ,  H01L2224/40137 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/84801 ,  H01L2224/8484 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H02M7/003 ,  H05K7/1432 ,  Y02T10/6217 ,  Y02T10/7022 ,  Y02T10/7077 ,  Y02T10/7241 ,  H01L2924/00014 ,  H01L2924/00

摘要： A power conversion apparatus includes a smoothing capacitor module having a plurality of one and the other DC terminals arranged in a state of being laminated with each other, a flow channel forming body for forming a cooling medium flow channel that allows a cooling medium to flow along the capacitor module, and a plurality of power semiconductor modules each including a module case having a cooling surface, DC terminals projecting in one direction in a laminated state from the module case, and an AC terminal projecting in one direction from the module case. The power semiconductor modules are fixed to the flow channel forming body so that the cooling surface of the module case of the power semiconductor module is inserted into the cooling medium flow channel and comes into contact with the cooling medium flowing within the flow channel forming body, and the respective DC terminals in the laminated state of the capacitor module extend from the capacitor module toward the corresponding power semiconductor modules, the laminated DC terminal includes a connecting portion in the direction along the flow channel, the respective connecting portions in the direction along the flow channels of the DC terminals of the capacitor module are respectively connected to the DC terminals projecting from the power semiconductor module in the direction across the cooling medium flow channel.

公开(公告)号：EP3005417A4

公开(公告)日：2017-08-30

申请号：EP14782292

申请日：2014-04-11

申请人： TEXAS INSTRUMENTS INC

发明人： DENISON MARIE ,  CARPENTER BRIAN ASHLEY ,  LOPEZ OSVALDO JORGE ,  HERBSOMMER JUAN ALEJANDRO ,  NOQUIL JONATHAN

IPC分类号： H01L27/02 ,  H01L23/495 ,  H01L25/07 ,  H05K1/02

CPC分类号： H01L23/49575 ,  H01L21/50 ,  H01L21/561 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49838 ,  H01L24/29 ,  H01L24/32 ,  H01L24/34 ,  H01L24/36 ,  H01L24/37 ,  H01L24/38 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/84 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/071 ,  H01L25/072 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/29101 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40139 ,  H01L2224/40145 ,  H01L2224/40245 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/84801 ,  H01L2224/8484 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01028 ,  H01L2924/014 ,  H01L2924/20752

摘要： A packaged multi-output converter (200) comprising a leadframe with a chip pad (201) as ground terminal and a plurality of leads (202) including the electrical input terminal (203); a first FET chip (sync chip, 220) with its source terminal affixed to the leadframe and on its opposite surface a first drain terminal (221) positioned adjacent to a second drain terminal (222), the drain terminals connected respectively by a first (241) and a second (242) metal clip to a first (204) and second (205) output lead; a second FET chip (control chip, 211), positioned vertically over the first drain terminal, with its source terminal attached onto the first clip; a third FET chip (control chip, 212), positioned vertically over the second drain terminal, with its source terminal attached onto the second clip; and the drain terminals (213, 214) of the second and third chips attached onto a third metal clip (260) connected to the input lead (203).

摘要翻译： 一种封装多输出转换器（200），包括具有作为接地端子的芯片焊盘（201）的引线框和包括电输入端子（203）的多个引线（202）; 第一FET芯片（同步芯片220），其源极端子固定到引线框架并且在其相对表面上与第二漏极端子（222）相邻定位的第一漏极端子（221），漏极端子分别通过第一（第二） （204）和第二输出引线（205）;以及第二（242）金属夹到第一输出引线（204）和第二输出引线（205） 第二FET芯片（控制芯片，211），其垂直地定位在第一漏极端子上方，其源极端子附接到第一夹子上; 第三FET芯片（控制芯片212），其垂直放置在第二漏极端子上方，其源极端子附接到第二夹子上; 和连接到与输入引线（203）连接的第三金属夹（260）上的第二和第三芯片的漏极端子（213,214）。

公开(公告)号：EP2720368A4

公开(公告)日：2015-11-18

申请号：EP12797538

申请日：2012-05-22

申请人： HITACHI AUTOMOTIVE SYSTEMS LTD

发明人： KANEKO YUJIRO ,  SUWA TOKIHITO ,  HIRAMITSU SHINJI ,  SHIMURA TAKAHIRO

IPC分类号： H02M7/48 ,  H01L23/373 ,  H01L23/473 ,  H05K7/20

CPC分类号： H05K7/20927 ,  B60L11/14 ,  B60L2200/26 ,  B60L2210/40 ,  H01L23/36 ,  H01L23/3736 ,  H01L23/473 ,  H01L24/36 ,  H01L24/40 ,  H01L2224/33 ,  H01L2224/40137 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/84801 ,  H01L2224/8484 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H02M7/003 ,  H02P27/06 ,  H02P29/60 ,  H05K7/209 ,  H05K7/20909 ,  Y02T10/70 ,  Y02T10/7077 ,  Y02T10/7241 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

公开(公告)号：EP2432014A4

公开(公告)日：2014-03-05

申请号：EP10774936

申请日：2010-05-12

申请人： ROHM CO LTD

发明人： YOSHIHARA KATSUHIKO ,  ISHII MASARU ,  KITAGURO KOUICHI

IPC分类号： H01L23/64 ,  H01L25/07 ,  H01L25/18

CPC分类号： H01L23/49844 ,  H01L23/315 ,  H01L23/3735 ,  H01L23/49822 ,  H01L23/645 ,  H01L24/32 ,  H01L24/33 ,  H01L24/34 ,  H01L24/36 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/72 ,  H01L24/73 ,  H01L25/072 ,  H01L2223/6611 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/32221 ,  H01L2224/32225 ,  H01L2224/37147 ,  H01L2224/40225 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48111 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/49111 ,  H01L2224/73251 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/84205 ,  H01L2224/85205 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1203 ,  H01L2924/12032 ,  H01L2924/12041 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/2076 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/32 ,  H01L2224/72

摘要： Disclosed is a semiconductor device having a structure capable of reducing the self-inductance of internal wiring. The semiconductor device includes: a lower board having a lower conductor layer formed on the surface thereof; a switching element bonded to the lower conductor layer in an element bonding area; a terminal bonded to the lower conductor layer in a terminal bonding area; an upper board stacked on the lower board in a board bonding area between the element bonding area and the terminal bonding area, and having an upper conductor layer on the surface thereof; and a switching element connecting member which connects the switching element with the upper conductor layer.

公开(公告)号：EP2526565A2

公开(公告)日：2012-11-28

申请号：EP10844172.6

申请日：2010-12-07

申请人： Vishay-Siliconix

发明人： JAUNAY, Serge ,  BELANI, Suresh ,  KUO, Frank ,  MAO, Sen ,  WANG, Peter

IPC分类号： H01L23/495 ,  H01L23/28

CPC分类号： H01L24/73 ,  H01L23/3107 ,  H01L23/49548 ,  H01L23/49562 ,  H01L24/16 ,  H01L24/32 ,  H01L24/36 ,  H01L24/40 ,  H01L24/97 ,  H01L2224/16245 ,  H01L2224/40245 ,  H01L2224/73253 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/37099

摘要： The present technology is directed toward semiconductors packaged by electrically coupling a plurality of die to an upper and lower lead frame. The opposite edges of each corresponding set of leads in the upper lead frame are bent. The leads in the upper lead frame are electrically coupled between respective contacts on respective die and respective lower portion of the leads in the lower lead frame. The bent opposite edges of each corresponding set of leads of the upper lead frame support the upper lead frame before encapsulation, for achieving a desired position of the plurality of die between the leads of the upper and lower lead frames in the packaged semiconductor. After the encapsulated die are separated, the upper leads have an L-shape and electrically couple die contacts on upper side of the die to leads on the lower side of the die so that the package contacts are on the same side of the semiconductor package.

公开(公告)号：EP2093793A2

公开(公告)日：2009-08-26

申请号：EP09250234.3

申请日：2009-01-28

申请人： Renesas Technology Corp.

发明人： Muto, Akira c/o Renesas Technology Corp., IP Property Div. ,  Koike, Nobuya c/o Renesas Technology Corp., IP Property Div. ,  Arai, Katsuo c/o Renesas Technology Corp., IP Property Div. ,  Fujiki, Atsushi c/o Renesas Technology Corp., IP Property Div.

IPC分类号： H01L21/56 ,  H01L23/31 ,  H01L23/495

CPC分类号： H01L21/565 ,  H01L23/3107 ,  H01L23/433 ,  H01L23/4334 ,  H01L23/49537 ,  H01L23/49551 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/29 ,  H01L24/33 ,  H01L24/36 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/83 ,  H01L25/115 ,  H01L25/117 ,  H01L2224/26145 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/29101 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/29499 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/40247 ,  H01L2224/4899 ,  H01L2224/73263 ,  H01L2224/83051 ,  H01L2224/83101 ,  H01L2224/83139 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/83855 ,  H01L2224/83862 ,  H01L2224/83885 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2225/1029 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01067 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/10253 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/07025 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/37099 ,  H01L2224/37599

摘要： The radiation performance of a resin sealed semiconductor package is enhanced and further the fabrication yield thereof is enhanced. A drain terminal coupled to the back surface drain electrode of a semiconductor chip is exposed at the back surfaceof an encapsulation resin section. Part of the following portion and terminal is exposed at the top surface of the encapsulation resin section: the first portion of a source terminal coupled to the source pad electrode of the semiconductor chip and a gate terminal coupled to the gate pad electrode of the semiconductor chip. The remaining part of the second portion of the source terminal and the gate terminal is exposed at the back surface of the encapsulation resin section. When this semiconductor device is manufactured, bonding material and a film member are placed between the drain terminal and the semiconductor chip. At the same time, paste-like bonding material and a film member are placed between the source terminal 3 and gate terminal and the semiconductor chip. The paste-like bonding material is cured and turned into bonding material. As the result of use of the film members, variation in the thickness of the bonding material is suppressed.

摘要翻译： 提高树脂密封半导体封装的放射性能，进一步提高其制造成品率。 耦合到半导体芯片的背表面漏电极的漏极端子在封装树脂部分的背面露出。 以下部分和端子的一部分暴露在封装树脂部分的顶表面处：耦合到半导体芯片的源极焊盘电极的源极端子的第一部分和耦合到半导体芯片的栅极焊盘电极的栅极端子 。 源极端子和栅极端子的第二部分的剩余部分在封装树脂部分的背面露出。 当制造该半导体器件时，将接合材料和膜部件置于漏极端子和半导体芯片之间。 同时，在源极端子3和栅极端子与半导体芯片之间放置糊状接合材料和膜部件。 糊状结合材料固化并变成粘结材料。 作为使用膜构件的结果，抑制了接合材料的厚度的变化。

公开(公告)号：EP1772900A2

公开(公告)日：2007-04-11

申请号：EP06020799.0

申请日：2006-10-04

申请人： Semikron Elektronik GmbH & Co. KG Patentabteilung

发明人： Heidenreich, Dirk ,  Stockmeier, Thomas, Dr.

IPC分类号： H01L21/60 ,  H01L25/07

CPC分类号： H01L23/492 ,  H01L24/27 ,  H01L24/33 ,  H01L24/36 ,  H01L24/40 ,  H01L24/48 ,  H01L24/83 ,  H01L25/072 ,  H01L25/50 ,  H01L2224/03003 ,  H01L2224/0311 ,  H01L2224/32225 ,  H01L2224/40095 ,  H01L2224/40225 ,  H01L2224/40491 ,  H01L2224/48491 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/84801 ,  H01L2224/8484 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/37099

摘要： Die Erfindung beschreibt eine Anordnung mit mindestens einem Leistungshalbleiterbauelement (70) und einem elektrisch isolierenden Gehäuse (3), sowie mit nach außen führenden Anschlusselementen (42,44,46) und mit einem vom Gehäuse zumindest teilweise umschlossenen Substrat (5). Das Leistungshalbleiterbauelement weist auf seiner dem Substrat abgewandten ersten Hauptfläche mindestens eine Kontaktfläche mit einer Metallisierungsschicht aus einem Edelmetall auf. Der Metallformkörper (76) weist auf seiner dem Leistungshalbleiterbauelement zugewandeten zweiten Hauptfläche ebenfalls eine Edelmetallschicht auf. Mittels einer Drucksinterverbindung sind diese miteinander verbunden.
Das zugehörige Herstellungsverfahren ist durch den wesentlichen Schritt gekennzeichnet, dass die Metallformkörper (76) auf den Leistungshalbleiterbauelementen (70) im Waferverbund angeordnet sind und eine Mehrzahl dieser Anordnungen gleichzeitig mit Druck (82) beaufschlagt werden und somit für mehrere dieser Anordnungen die Drucksinterverbindung gleichzeitig erzeugt wird.

摘要翻译： 该模块具有功率半导体元件（70），并且在电绝缘壳体，其中，所述组件在其主表面的衬底布置。 该组件具有与贵金属的金属化层的接触表面E.G. 金，在另一主表面并从所述衬底拒之门外。 的接触面和金属模具主体（76）是由一个功率烧结连接，其中所述主体具有面对所述部件前者主要层上的贵金属层相互连接。 因此独立claimsoft包括用于制造装置的方法。

公开(公告)号：EP1589632A3

公开(公告)日：2006-10-18

申请号：EP05007951.6

申请日：2005-04-12

申请人： Hitachi, Ltd.

发明人： Shirakawa, Shinji ,  Mori, Mutsuhiro ,  Inaba, Masamitsu ,  Yamauchi, Tatsumi ,  Iwamura, Masahiro ,  Mashino, Keiichi ,  Tsuchiya, Masanori

IPC分类号： H02J7/14 ,  F02N11/08 ,  H01L29/00

CPC分类号： F02N11/04 ,  B60K6/26 ,  B60K6/48 ,  B60W10/08 ,  F02D2041/2075 ,  F02N11/0814 ,  F02N11/0859 ,  F02N2011/0896 ,  H01L24/36 ,  H01L24/40 ,  H01L24/41 ,  H01L2224/32225 ,  H01L2224/40225 ,  H01L2224/4103 ,  H01L2924/00014 ,  H01L2924/13055 ,  H01L2924/13091 ,  H02J7/1492 ,  H02M7/003 ,  Y02T10/6221 ,  Y02T10/7005 ,  H01L2924/00 ,  H01L2224/37099

摘要： The invention relates to an inverter device (50) which is mounted on the rotating electric machine body (1). The inverter device (50) includes a module unit (52) having a converter circuit (53) and a control unit (51) that controls the operation of the converter circuit (55). The converter circuit (55) is configured by connecting a plurality of the following series circuits in parallel, each of the series circuits includes a P-channel MOS semiconductor device disposed at a higher potential side and an N-channel MOS semiconductor device disposed at a lower potential side which are electrically connected in series. An electric power that is supplied from a battery (150) or an electric power that is supplied to the battery (150) is controlled.

公开(公告)号：EP1599078A3

公开(公告)日：2006-10-11

申请号：EP05004621.8

申请日：2005-03-03

申请人： Semikron Elektronik GmbH & Co. KG Patentabteilung

发明人： Palm, Gerhard

IPC分类号： H05K3/34 ,  B23K3/06 ,  B23K35/02 ,  H01L21/68 ,  H01L21/60

CPC分类号： H01L24/33 ,  B22F2998/00 ,  B23K35/025 ,  B23K35/3006 ,  H01L21/6835 ,  H01L24/27 ,  H01L24/29 ,  H01L24/36 ,  H01L24/40 ,  H01L24/83 ,  H01L2221/68354 ,  H01L2221/68363 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/83005 ,  H01L2224/83191 ,  H01L2224/83201 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01068 ,  H01L2924/01322 ,  H01L2924/1301 ,  H01L2924/19043 ,  H05K3/321 ,  H05K2201/10984 ,  H05K2203/0156 ,  H05K2203/0278 ,  H05K2203/0338 ,  H05K2203/1131 ,  B22F7/064 ,  H01L2924/00 ,  H01L2224/37099

摘要： Die Erfindung beschreibt zwei Verfahren zur Befestigung von elektronischen Bauelementen, insbesondere von Leistungshalbleiterbauelementen wie Dioden, Transistoren oder Thyristoren, und von Anschlusselementen mittels Drucksintern mit den Verfahrensschritten des ersten Verfahrens: Aufbringen einer aus einem Metallpulver und einem Lösungsmittel bestehenden pastösen Schicht (20) auf eine Trägerfolie (10); Trocknen der pastösen Schicht; Aufbringen von mindestens einem Bauelement (40) auf die getrocknete Schicht; Druckbeaufschlagung des Verbunds aus dem mindestens einen Bauelement und der Trägerfolie mit der getrockneten Schicht, wodurch die Haftkraft zwischen der Schicht (20) und dem Bauelement (40) größer wird als zwischen der Schicht (20) und der Trägerfolie (10); Abheben des mindestens einen Bauelements (40) mit daran haftender Schicht (20") von der Trägerfolie (10); Positionierung des Bauelements (40) mit der daran haftenden Schicht (20") auf dem Substrat (50); Druckbeaufschlagung der Anordnung des Substrats (50) und des Bauelements (40) zu deren Sinterverbindung.

摘要翻译： 电子部件通过使电子部件，支撑膜和糊状层受到压力而固定到基板上，使得干燥层和部件之间的粘合力变得大于干燥层和支撑膜之间的粘合力; 并对基板和部件进行压力，从而通过烧结连接基板和部件。 通过压力烧结将电子部件固定到基板上包括：（a）将包含金属粉末和溶剂的糊状层（20）施加到支撑膜（10）上; （b）干燥糊状层; 将电子部件施加到干燥层上; （c）使电子部件，支撑膜和干燥层受压，使得干燥层和部件之间的粘合力变得大于干燥层和支撑膜之间的粘合力; （d）从附着膜去除附着在该部件上的层的部件; （e）将所述部件定位在所述基板上; 和（f）使基板和部件受压，从而通过烧结连接基板和部件。