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公开(公告)号:JP5178899B2
公开(公告)日:2013-04-10
申请号:JP2011233277
申请日:2011-10-24
Applicant: 太陽誘電株式会社
CPC classification number: H05K1/0284 , H01F2017/0046 , H01F2017/0073 , H01P1/213 , H01P3/003 , H05K1/0219 , H05K1/0253 , H05K1/162 , H05K1/165 , H05K1/185 , H05K3/4608 , H05K2201/0338 , H05K2201/09745
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32.
公开(公告)号:JP5144657B2
公开(公告)日:2013-02-13
申请号:JP2009517850
申请日:2008-05-30
Applicant: 京セラ株式会社
IPC: H01L23/36
CPC classification number: H05K1/0203 , C04B37/006 , C04B2237/124 , C04B2237/368 , H01L23/3735 , H01L24/48 , H01L2224/451 , H01L2224/48091 , H01L2224/48227 , H01L2924/00011 , H01L2924/00014 , H01L2924/00015 , H01L2924/01012 , H01L2924/01019 , H01L2924/01068 , H01L2924/12042 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H05K1/0306 , H05K1/144 , H05K3/0061 , H05K3/388 , H05K2201/0338 , H05K2201/042 , H05K2201/066 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2924/01033
Abstract: A laminated heat dissipating base body (1) includes first and second bases (21, 22) having insulation properties arranged one above the other to face each other; a heat dissipating member (42) sandwiched between the first and second bases (21, 22); and circuit members (41) disposed on a top surface of the first base (21) arranged above and a bottom surface of the second base (22) arranged below, respectively. A bonding member is interposed at least either between the first base (21) and the heat dissipating member (42) or between the second base (22) and the circuit member (41), and includes an active metal layer (31, 32) containing an active metal disposed on the first and/or second base (21, 22) side thereof, and a bonding layer (51, 52) containing a metal disposed at least either on the heat dissipating member (42) side thereof or on the circuit member (41) side thereof.
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公开(公告)号:JPWO2010147059A1
公开(公告)日:2012-12-06
申请号:JP2011519752
申请日:2010-06-11
Applicant: Jx日鉱日石金属株式会社 , Jx日鉱日石金属株式会社
CPC classification number: H05K3/06 , H05K1/09 , H05K2201/0338 , H05K2201/098
Abstract: 樹脂基板の片面または両面に形成された銅又は銅合金の層(A)、該A層上の一部または全面に形成された銅又は銅合金の層(B)、該(B)層上の一部又は全面に形成された銅エッチング液に対して銅よりもエッチング速度が遅い層(C)を有し、エッチングにより(A)層と(B)層及び(C)層の一部を除去することにより形成された銅回路からなり、該銅回路間に形成された樹脂基板上のスペースが、前記(A)層及び(B)層を合わせた銅の厚みに応じた幅に調整されていることを特徴とする電子回路。回路幅の均一な回路を形成でき、パターンエッチングでのエッチング性の向上、ショートや回路幅の不良の発生を防止することを課題とする。
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公开(公告)号:JP2012525716A
公开(公告)日:2012-10-22
申请号:JP2012508622
申请日:2010-04-28
Inventor: ジュアン・カルロス・フィゲロア , ダミアン・フランシス・リアドン
CPC classification number: H01G4/008 , H01G4/085 , H01G4/12 , H01G4/33 , H01L28/40 , H05K1/09 , H05K1/162 , H05K2201/0338 , H05K2201/0355 , H05K2203/0361 , Y10T29/43
Abstract: キャパシタを製造するための方法が提供される。 本方法において、誘電体が金属(例えばニッケル)基板上に形成されてもよく、銅電極がその上に形成され、その後に、金属基板の、そのコートされていない面から薄化が行なわれ、次いで、基板の薄化されたコートされていない面上に銅電極を形成する。
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公开(公告)号:JP2012186431A
公开(公告)日:2012-09-27
申请号:JP2011050361
申请日:2011-03-08
Inventor: SEKINE SHIGENOBU , SEKINE YURINA
CPC classification number: H05K1/097 , H01L23/49866 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/81 , H01L24/83 , H01L25/0657 , H01L31/022425 , H01L31/0682 , H01L33/62 , H01L2224/16145 , H01L2224/16225 , H01L2224/2929 , H01L2224/293 , H01L2224/81191 , H01L2224/81193 , H01L2224/81395 , H01L2224/81903 , H01L2224/83191 , H01L2224/83192 , H01L2224/8359 , H01L2224/83605 , H01L2224/83609 , H01L2224/83611 , H01L2224/83613 , H01L2224/83618 , H01L2224/83624 , H01L2224/83639 , H01L2224/83644 , H01L2224/83647 , H01L2224/83655 , H01L2224/8366 , H01L2224/83666 , H01L2224/83669 , H01L2224/83701 , H01L2224/83799 , H01L2224/83815 , H01L2224/83825 , H01L2224/83851 , H01L2224/83886 , H01L2225/06517 , H01L2225/06541 , H01L2225/06572 , H01L2924/00011 , H01L2924/01327 , H01L2924/12041 , H01L2924/14 , H01L2924/1431 , H01L2924/1434 , H05K1/111 , H05K2201/0338 , H05K2201/099 , Y02E10/547 , Y02P70/611 , H01L2924/00 , H01L2224/8159 , H01L2924/00014 , H01L2224/81799 , H01L2924/00012 , H01L2224/81639 , H01L2224/81647 , H01L2224/81644 , H01L2224/81669 , H01L2224/81666 , H01L2224/81624 , H01L2224/81618 , H01L2224/8166 , H01L2224/81655 , H01L2224/81611 , H01L2224/81609 , H01L2224/81613 , H01L2224/81605 , H01L2224/29075
Abstract: PROBLEM TO BE SOLVED: To provide an electronic apparatus which is excellent in conductivity, electrochemical stability, oxidation resistance, repletion, denseness, and mechanical and physical strength and has a high quality metalization wiring having high bonding and adhesive force to substrates and achieving high reliability.SOLUTION: A substrate 11 has metalization wiring 12 having a predetermined pattern. The metalization wiring 12 includes a metalization layer 121 and an insulation layer 122. The metalization layer 121 includes a high melting metal component and a low melting metal component, and the high melting metal component and the low melting metal component are diffusively joined to each other. The insulation layer 122 is formed at the same time as the metalization layer 121 and covers an exterior surface of the metalization layer 121. An electronic component 14 electrically connects with the metalization layer 121 of the metalization wiring 12.
Abstract translation: 要解决的问题:提供导电性,电化学稳定性,抗氧化性,补充性,致密性和机械和物理强度优异的电子设备,并且具有对基底具有高粘合力和粘合力的高质量金属化布线, 实现高可靠性。 解决方案:基板11具有预定图案的金属化布线12。 金属化布线12包括金属化层121和绝缘层122.金属化层121包括高熔点金属成分和低熔点金属成分,高熔点金属成分和低熔点金属成分彼此扩散接合 。 绝缘层122与金属化层121同时形成并覆盖金属化层121的外表面。电子部件14与金属化布线12的金属化层121电连接。(C )2012,JPO&INPIT
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公开(公告)号:JP5025158B2
公开(公告)日:2012-09-12
申请号:JP2006124084
申请日:2006-04-27
Applicant: 日立造船株式会社
IPC: B23K26/06 , B23K26/067 , B23K101/42 , H05K3/00
CPC classification number: B23K26/0604 , B23K26/0006 , B23K26/0608 , B23K26/0676 , B23K2201/42 , B23K2203/00 , B23K2203/56 , H05K3/0026 , H05K3/027 , H05K2201/0338 , H05K2203/108
Abstract: [PROBLEMS] The present invention provides a method and an apparatus for efficiently processing in patterning of an electronic circuit board even when laser beams of differing intensities and wavelengths are irradiated in multiple stages. [MEANS FOR SOLVING PROBLEMS] A laser processing apparatus is provided with first and second laser oscillators (2a, 2b) for emitting laser beams (3a, 3b) of which at least the wavelength or the intensities are different from each other; a stage apparatus (5) for moving a workpiece (1) to be processed; and optical systems (4a, 4b) for guiding the laser beams (3a, 3b) to prescribed positions of the workpiece (1). The optical systems (4a, 4b) can be moved by means of an adjusting device (6) according to the relative moving direction of the laser beams (3a, 3b) and the workpiece (1) to permit the prescribed position of the workpiece (1) to be irradiated with laser beams (3a, 3b) in that order so that the workpiece (1) can be processed by the laser beams (3a, 3b). Thus, efficient laser processing can be performed without limiting the relative moving direction of the laser beams and the workpiece and without unnecessary movement.
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公开(公告)号:JP2012060121A
公开(公告)日:2012-03-22
申请号:JP2011192424
申请日:2011-09-05
Inventor: MUN JON-HO , OH SAN-HYOK
IPC: H05K3/42
CPC classification number: C25D7/123 , H01L2924/0002 , H05K3/423 , H05K3/427 , H05K2201/0338 , H05K2203/1476 , H01L2924/00
Abstract: PROBLEM TO BE SOLVED: To reduce the deviation in plating thickness of a copper plated layer filling a circuit pattern part and a through-hole part in a SIP product group with a narrow through-hole pitch and a large through-hole volume.SOLUTION: A method for forming a plated layer of a printed board comprises: a step of forming a through-hole for a CCL (Copper clad lamination) 10; a step of forming a seed plated layer 20 at the through-hole; a step of coating the CCL 10 and the seed plated layer 20 with a resist 40; a step of light-exposing and developing the resist 40 on the seed plated layer 20; a step of forming a primary plated layer 50 on the seed plated layer 20; a step of forming a copper plated layer 60 on the primary plated layer 50; and a step of forming a circuit pattern 61 by removing the resist 40 and the seed plated layer 20 remaining on the primary plated layer 50.
Abstract translation: 要解决的问题:为了减少填充具有窄通孔间距和大通孔容积的SIP产品组中的电路图形部分和通孔部分的镀铜层的电镀厚度的偏差 。 解决方案:一种用于形成印刷电路板的镀层的方法,包括:形成用于CCL(覆铜层压)10的通孔的步骤; 在通孔处形成种子镀层20的步骤; 用抗蚀剂40涂覆CCL 10和种子镀层20的步骤; 在种子镀层20上曝光和显影抗蚀剂40的步骤; 在种皮镀层20上形成初级镀层50的工序; 在主镀层50上形成镀铜层60的工序; 以及通过去除残留在主镀层50上的抗蚀剂40和种子镀层20形成电路图案61的步骤。(C)2012,JPO&INPIT
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38.
公开(公告)号:JP2011228609A
公开(公告)日:2011-11-10
申请号:JP2010143505
申请日:2010-06-24
Applicant: Samsung Electro-Mechanics Co Ltd , Snu R & Db Foundation , エスエヌユー アールアンドディービー ファウンデーション , サムソン エレクトロ−メカニックス カンパニーリミテッド.
Inventor: HYUNG WOOK PARK , CHOI YOUNG CHAN , MIN HONG SEOK , KO YEONG GWON , YU CHANG SEOP , LEE HOYEON , LEE SIN BOK , CHOI MIN SEOK
CPC classification number: H05K3/244 , H05K2201/0338 , H05K2201/0769 , Y10T29/49126 , Y10T29/49155
Abstract: PROBLEM TO BE SOLVED: To provide a printed circuit substrate that can suppress short-circuiting due to electrochemical migration to achieve high-density and improve reliability, and to provide a method of manufacturing the same.SOLUTION: The printed circuit substrate and method of manufacturing the same according to the present invention relate to a printed circuit substrate including an insulating layer, and a circuit pattern disposed on the insulating layer and a barrier layer that is disposed to cover at least one surface of the circuit pattern and suppresses electrochemical migration from the circuit pattern, thereby making it possible to achieve high-density besides securing reliability, and relate to the method of manufacturing the same.
Abstract translation: 要解决的问题:提供能够抑制由于电化学迁移引起的短路以实现高密度并提高可靠性的印刷电路基板,并提供其制造方法。 解决方案:根据本发明的印刷电路基板及其制造方法涉及包括绝缘层的印刷电路基板和设置在绝缘层上的电路图案和设置成覆盖在绝缘层上的阻挡层 电路图案的至少一个表面,并且抑制从电路图案的电化学迁移,从而除了确保可靠性之外还可以实现高密度,并且涉及其制造方法。 版权所有(C)2012,JPO&INPIT
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公开(公告)号:JP2011053651A
公开(公告)日:2011-03-17
申请号:JP2010133234
申请日:2010-06-10
Applicant: Samsung Mobile Display Co Ltd , 三星モバイルディスプレイ株式會社
Inventor: LEE JUNG-MIN , LEE CHOONG-HO
CPC classification number: H01L27/3276 , H05K3/323 , H05K2201/0133 , H05K2201/0221 , H05K2201/0338 , H05K2201/10674
Abstract: PROBLEM TO BE SOLVED: To provide a display device capable of suppressing an increase in contact resistance between a substrate and an integrated circuit chip by fixing the compressed form of a conductive ball. SOLUTION: The display device includes: a wiring substrate having a wiring part formed therein; an integrated circuit chip mounted on the wiring substrate; and a pad part extended from the wiring part to be set between the wiring substrate and the integrated circuit chip, and coupled to the integrated circuit chip. The pad part includes: a first conductive layer extended from the wiring part; and a second conductive layer positioned on the first conductive layer and harder than the first conductive layer. COPYRIGHT: (C)2011,JPO&INPIT
Abstract translation: 解决的问题:提供一种能够通过固定导电球的压缩形式来抑制基板和集成电路芯片之间的接触电阻增加的显示装置。 解决方案:显示装置包括:布线基板,其中形成有布线部分; 安装在所述布线基板上的集成电路芯片; 以及从布线部分延伸以设置在布线基板和集成电路芯片之间的焊盘部分,并且耦合到集成电路芯片。 焊盘部分包括:从布线部分延伸的第一导电层; 以及位于所述第一导电层上并且比所述第一导电层硬的第二导电层。 版权所有(C)2011,JPO&INPIT
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40.
公开(公告)号:JP2011029178A
公开(公告)日:2011-02-10
申请号:JP2010151205
申请日:2010-07-01
Applicant: Hitachi Chem Co Ltd , 日立化成工業株式会社
Inventor: TAKAI KENJI , EJIRI YOSHINORI , NAGAHARA YUKO , MATSUZAWA MITSUHARU
CPC classification number: H05K3/323 , B22F1/0062 , B22F1/025 , B22F2998/10 , H05K2201/0221 , H05K2201/0224 , H05K2201/0338 , B22F1/02
Abstract: PROBLEM TO BE SOLVED: To inexpensively provide a conductive particle for providing an anisotropic conductive adhesive capable of maintaining a sufficient insulating characteristic and conduction characteristic even in connection of a microcircuit, and excellent in anti-hygroscopicity.
SOLUTION: This coated conductive particle 5 includes a composite conductive particle 3 having a resin particle 4 and a metal layer 6 for coating the resin particle 4, and an insulating fine particle 1 provided in an outside of the metal layer 6, and for coating one part of a surface of the metal layer 6. The metal layer 6 includes a nickel-palladium alloy plated layer 6a.
COPYRIGHT: (C)2011,JPO&INPITAbstract translation: 要解决的问题:为了廉价地提供一种用于提供能够保持足够的绝缘特性和导电特性的各向异性导电粘合剂的导电颗粒,即使在微电路的连接和抗吸湿性也优异的情况下。 <解决方案>该涂覆导电粒子5包括具有树脂颗粒4和用于涂覆树脂颗粒4的金属层6的复合导电颗粒3和设置在金属层6外侧的绝缘细颗粒1,以及 用于涂覆金属层6的一部分表面。金属层6包括镍 - 钯合金镀层6a。 版权所有(C)2011,JPO&INPIT
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