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35 条记录 (耗时 0.021 秒)

    Semiconductor device
    1.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US07576406B2

    公开(公告)日：2009-08-18

    申请号：US10773658

    申请日：2004-02-09

    申请人： Yoichi Tamaki ,  Hideaki Nonami ,  Masato Hamamoto

    发明人： Yoichi Tamaki ,  Hideaki Nonami ,  Masato Hamamoto

    IPC分类号： H01L29/00

    CPC分类号： H01L27/0823

    摘要： A plurality of the same kind of npn-type bipolar transistors are disposed regularly on a semiconductor layer that is provided over an insulation layer. The plurality of unit bipolar transistors are connected in parallel, thereby to form a plurality of desired bipolar transistors. A deep trench isolation surrounds a group of or the whole of the plurality of unit bipolar transistors that are connected in parallel, for a plurality of desired bipolar transistor that require thermal stability.

    摘要翻译： 多个相同种类的npn型双极晶体管规则地设置在设置在绝缘层上的半导体层上。 多个单位双极晶体管并联连接，从而形成多个希望的双极晶体管。 对于需要热稳定性的多个所需双极晶体管，深沟槽隔离围绕并联连接的多个单元双极晶体管的一组或全部。

    Semiconductor device and process of producing the same
    3.
    发明授权
    Semiconductor device and process of producing the same 失效
    半导体器件及其制造方法

    公开(公告)号：US06835632B2

    公开(公告)日：2004-12-28

    申请号：US10460215

    申请日：2003-06-13

    申请人： Hiromi Shimamoto ,  Takashi Uchino ,  Takeo Shiba ,  Kazuhiro Ohnishi ,  Yoichi Tamaki ,  Takashi Kobayashi ,  Toshiyuki Kikuchi ,  Takahide Ikeda

    发明人： Hiromi Shimamoto ,  Takashi Uchino ,  Takeo Shiba ,  Kazuhiro Ohnishi ,  Yoichi Tamaki ,  Takashi Kobayashi ,  Toshiyuki Kikuchi ,  Takahide Ikeda

    IPC分类号： H01L2120

    CPC分类号： H01L27/0652 ,  H01L27/0688 ,  H01L28/20

    摘要： The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistance while the second polycrystalline silicon layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.

    摘要翻译： 本发明提供了一种其电阻值被控制的多晶硅导电结构（例如电阻器），并且可以相对于任何电阻值而言可以变化较小并且对温度的依赖性较小，及其制造方法。 使用至少包括具有大晶粒尺寸的第一多晶硅层和小晶粒尺寸的第二多晶硅层的两层结构，并且第一多晶硅层具有正的温度对电阻的依赖性，而第二多晶硅层的第二 多晶硅层具有负电阻的温度依赖性，反之亦然。 此外，可以通过高剂量离子注入和退火，或者通过在不同温度下的化学气相沉积来沉积这些层，形成大晶粒和小晶粒层，可以形成大晶粒尺寸的多晶硅层。

    Semiconductor device and process of producing the same
    5.
    发明授权
    Semiconductor device and process of producing the same 失效
    半导体器件及其制造方法

    公开(公告)号：US06524924B1

    公开(公告)日：2003-02-25

    申请号：US09123406

    申请日：1998-07-28

    申请人： Hiromi Shimamoto ,  Takashi Uchino ,  Takeo Shiba ,  Kazuhiro Ohnishi ,  Yoichi Tamaki ,  Takashi Kobayashi ,  Toshiyuki Kikuchi ,  Takahide Ikeda

    发明人： Hiromi Shimamoto ,  Takashi Uchino ,  Takeo Shiba ,  Kazuhiro Ohnishi ,  Yoichi Tamaki ,  Takashi Kobayashi ,  Toshiyuki Kikuchi ,  Takahide Ikeda

    IPC分类号： H01L2120

    CPC分类号： H01L27/0652 ,  H01L27/0688 ,  H01L28/20

    摘要： The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistances while the second polycrystalline layer has a negative temperature dependance of resistance, or vise versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.

    摘要翻译： 本发明提供了一种其电阻值被控制的多晶硅导电结构（例如电阻器），并且可以相对于任何电阻值而言可以变化较小并且对温度的依赖性较小，及其制造方法。 使用包括具有大晶粒尺寸的第一多晶硅层和小晶粒尺寸的第二多晶硅层的至少两层结构，并且第一多晶硅层具有正电温度依赖性而第二 多晶层具有电阻的负温度依赖性，反之亦然。 此外，可以通过高剂量离子注入和退火，或者通过在不同温度下的化学气相沉积来沉积这些层，形成大晶粒和小晶粒层，可以形成大晶粒尺寸的多晶硅层。

    Method for fabricating a semiconductor integrated circuit device having thick oxide films and groove etch and refill
    7.
    发明授权
    Method for fabricating a semiconductor integrated circuit device having thick oxide films and groove etch and refill 失效
    用于制造具有厚氧化膜和凹槽蚀刻和再填充的半导体集成电路器件的方法

    公开(公告)号：US4853343A

    公开(公告)日：1989-08-01

    申请号：US169748

    申请日：1988-03-18

    申请人： Akihisa Uchida ,  Daisuke Okada ,  Toshihiko Takakura ,  Katsumi Ogiue ,  Yoichi Tamaki ,  Masao Kawamura

    发明人： Akihisa Uchida ,  Daisuke Okada ,  Toshihiko Takakura ,  Katsumi Ogiue ,  Yoichi Tamaki ,  Masao Kawamura

    IPC分类号： H01L21/316 ,  H01L21/331 ,  H01L21/76 ,  H01L21/762 ,  H01L21/763 ,  H01L21/768 ,  H01L23/522 ,  H01L29/73

    CPC分类号： H01L21/76224 ,  H01L21/76 ,  H01L21/76202 ,  H01L21/763 ,  H01L2924/0002 ,  Y10S438/981

    摘要： A semiconductor device employing a new isolation process is disclosed, wherein an isolation area is a region in which a burying material is buried in a deep groove formed in a semiconductor body with a substantially constant width by anisotropic dry etching, semiconductor elements are formed in selected ones of semiconductor regions isolated by the isolation area, and others of the semiconductor regions, with no semiconductor element formed therein, have their whole surface covered with a thick oxide film which is produced by the local oxidation of the semiconductor body.The new isolation process is well-suited for a bipolar type semiconductor device, wherein the deep groove is formed so as to reach a semiconductor substrate through an N.sup.+ -type buried layer, and a thick oxide film formed simultaneously with the aforementioned thick oxide film isolates the base region and collector contact region of a bipolar transistor.

    摘要翻译： 公开了一种采用新的隔离工艺的半导体器件，其中隔离区域是通过各向异性干法蚀刻将掩埋材料埋入形成在半导体主体中的宽度基本恒定的深沟槽的区域，半导体元件形成为选定的 通过隔离区域隔离的半导体区域以及其中没有形成半导体元件的其它半导体区域，其全部表面被由半导体本体的局部氧化产生的厚氧化膜覆盖。 新的隔离工艺非常适用于双极型半导体器件，其中深沟形成为通过N +型掩埋层到达半导体衬底，并且与上述厚氧化膜隔离物同时形成的厚氧化膜 双极晶体管的基极区域和集电极接触区域。

    Isolation regions formed by locos followed with groove etch and refill
    8.
    发明授权
    Isolation regions formed by locos followed with groove etch and refill 失效
    由区域形成的隔离区域随后进行凹槽蚀刻和再填充

    公开(公告)号：US4746963A

    公开(公告)日：1988-05-24

    申请号：US946778

    申请日：1986-12-29

    申请人： Akihisa Uchida ,  Daisuke Okada ,  Toshihiko Takakura ,  Katsumi Ogiue ,  Yoichi Tamaki ,  Masao Kawamura

    发明人： Akihisa Uchida ,  Daisuke Okada ,  Toshihiko Takakura ,  Katsumi Ogiue ,  Yoichi Tamaki ,  Masao Kawamura

    IPC分类号： H01L21/316 ,  H01L21/331 ,  H01L21/76 ,  H01L21/762 ,  H01L21/763 ,  H01L21/768 ,  H01L23/522 ,  H01L29/73 ,  H01L21/95

    CPC分类号： H01L21/76224 ,  H01L21/76 ,  H01L21/76202 ,  H01L21/763 ,  H01L2924/0002 ,  Y10S438/981

    摘要： A semiconductor device employing a new isolation process is disclosed, wherein an isolation area is a region in which a burying material is buried in a deep groove formed in a semiconductor body with a substantially constant width by anisotropic dry etching, semiconductor elements are formed in selected ones of semiconductor regions isolated by the isolation area, and others of the semiconductor regions, with no semiconductor element formed therein, have their whole surface covered with a thick oxide film which is produced by the local oxidation of the semiconductor body. The new isolation process is well-suited for a bipolar type semiconductor device, wherein the deep groove is formed so as to reach a semiconductor substrate through an N.sup.+ -type buried layer, and a thick oxide film formed simultaneously with the aforementioned thick oxide film isolates the base region and collector contact region of a bipolar transistor.

    摘要翻译： 公开了一种采用新的隔离工艺的半导体器件，其中隔离区域是通过各向异性干法蚀刻将掩埋材料埋入形成在半导体主体中的宽度基本恒定的深沟槽的区域，半导体元件形成为选定的 通过隔离区域隔离的半导体区域以及其中没有形成半导体元件的其它半导体区域，其全部表面被由半导体本体的局部氧化产生的厚氧化膜覆盖。 新的隔离工艺非常适用于双极型半导体器件，其中深沟形成为通过N +型掩埋层到达半导体衬底，并且与上述厚氧化膜隔离物同时形成的厚氧化膜 双极晶体管的基极区域和集电极接触区域。

    Semiconductor device and process of producing the same
    9.
    发明授权
    Semiconductor device and process of producing the same 失效
    半导体器件及其制造方法

    公开(公告)号：US06610569B1

    公开(公告)日：2003-08-26

    申请号：US09649504

    申请日：2000-08-28

    申请人： Hiromi Shimamoto ,  Takashi Uchino ,  Takeo Shiba ,  Kazuhiro Ohnishi ,  Yoichi Tamaki ,  Takashi Kobayashi ,  Toshiyuki Kikuchi ,  Takahide Ikeda

    发明人： Hiromi Shimamoto ,  Takashi Uchino ,  Takeo Shiba ,  Kazuhiro Ohnishi ,  Yoichi Tamaki ,  Takashi Kobayashi ,  Toshiyuki Kikuchi ,  Takahide Ikeda

    IPC分类号： H01L21336

    CPC分类号： H01L27/0652 ,  H01L27/0688 ,  H01L28/20

    摘要： The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the polycrystalline first silicon layer has a positive in temperature dependence of resist while the second polycrystalline layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.

    摘要翻译： 本发明提供了一种其电阻值被控制的多晶硅导电结构（例如电阻器），并且可以相对于任何电阻值而言可以变化较小并且对温度的依赖性较小，及其制造方法。 使用至少包括具有大晶粒尺寸的第一多晶硅层和小晶粒尺寸的第二多晶硅层的两层结构，并且多晶第一硅层的抗蚀剂的温度依赖性为正，而 第二多晶层具有电阻的负温度依赖性，反之亦然。 此外，可以通过高剂量离子注入和退火，或者通过在不同温度下的化学气相沉积来沉积这些层，形成大晶粒和小晶粒层，可以形成大晶粒尺寸的多晶硅层。