公开(公告)号：US11967559B2

公开(公告)日：2024-04-23

申请号：US17535400

申请日：2021-11-24

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chang Chi Lee ,  Chiu-Wen Lee ,  Jung Jui Kang

IPC: H01L23/538 ,  H01L25/065

CPC classification number: H01L23/5384 ,  H01L23/5386 ,  H01L25/0655

Abstract: An electronic package is provided. The electronic package includes a semiconductor substrate. The semiconductor substrate includes a first active region and a first passive region separated from the first active region. The first active region is configured to regulate a power signal. The first passive region is configured to transmit a data signal.

公开(公告)号：US11594518B2

公开(公告)日：2023-02-28

申请号：US17338600

申请日：2021-06-03

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chang Chi Lee ,  Jung Jui Kang ,  Chiu-Wen Lee ,  Li Chieh Chen

IPC: H01L25/065 ,  H01L23/538

Abstract: A semiconductor package and a method for manufacturing a semiconductor package are provided. The semiconductor package includes a first processing element, a first I/O element, a second processing element, and a second I/O element. The first processing element is on a substrate. The first I/O element is on the substrate and electrically connected to the first processing element. The second processing element is on the substrate. The second I/O element is on the substrate and electrically connected to the second processing element. The first I/O element is electrically connected to and physically separated from the second I/O element.

公开(公告)号：US12107074B2

公开(公告)日：2024-10-01

申请号：US18115743

申请日：2023-02-28

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chang Chi Lee ,  Jung Jui Kang ,  Chiu-Wen Lee ,  Li Chieh Chen

IPC: H01L25/065 ,  H01L23/538

CPC classification number: H01L25/0655 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5387

Abstract: A semiconductor package and a method for manufacturing a semiconductor package are provided. The semiconductor package includes a first processing element, a first I/O element, a second processing element, and a second I/O element. The first processing element is on a substrate. The first I/O element is on the substrate and electrically connected to the first processing element. The second processing element is on the substrate. The second I/O element is on the substrate and electrically connected to the second processing element. The first I/O element is electrically connected to and physically separated from the second I/O element.

公开(公告)号：US09953930B1

公开(公告)日：2018-04-24

申请号：US15299236

申请日：2016-10-20

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Ying-Ta Chiu ,  Chiu-Wen Lee ,  Dao-Long Chen ,  Po-Hsien Sung ,  Ping-Feng Yang ,  Kwang-Lung Lin

IPC: H01L21/00 ,  H01L23/10 ,  H01L23/552

CPC classification number: H01L23/60 ,  H01L21/56 ,  H01L21/565 ,  H01L23/06 ,  H01L23/10 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/552 ,  H01L24/49 ,  H01L2224/48091

Abstract: A semiconductor package structure includes a substrate, a semiconductor element, an encapsulant, an adhesion layer and a metal cap. The semiconductor element is disposed on the substrate. The encapsulant covers the semiconductor element. The adhesion layer is disposed on the encapsulant. The metal cap is attached to the encapsulant by the adhesion layer, and the metal cap is conformal with the encapsulant.

公开(公告)号：US11127650B2

公开(公告)日：2021-09-21

申请号：US16799751

申请日：2020-02-24

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien Lin Chang Chien ,  Chiu-Wen Lee ,  Hung-Jung Tu ,  Chang Chi Lee ,  Chin-Li Kao

IPC: H01L23/36 ,  H01L21/48 ,  H01L23/48 ,  H01L23/367 ,  H01L23/00

Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a first die, a second die, and a thermal dissipation element. The first die has a first surface. The second die is disposed on the first surface. The thermal dissipation element is disposed on the first surface. The thermal dissipation element includes a first portion extending in a first direction substantially parallel to the first surface and partially covered by the second die and a second portion extending in a second direction substantially perpendicular to the first surface to be adjacent to an edge of the second die.

公开(公告)号：US09443813B1

公开(公告)日：2016-09-13

申请号：US14639535

申请日：2015-03-05

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yu-Hsiang Hsiao ,  Chiu-Wen Lee ,  Ping-Feng Yang ,  Kwang-Lung Lin

IPC: H01L23/00

CPC classification number: H01L24/13 ,  B23K1/0016 ,  B23K35/262 ,  B23K35/302 ,  B23K2101/40 ,  C22C9/02 ,  C22C13/00 ,  H01L24/05 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05147 ,  H01L2224/05572 ,  H01L2224/1182 ,  H01L2224/13025 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/13611 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/13686 ,  H01L2224/16146 ,  H01L2224/16503 ,  H01L2224/16507 ,  H01L2224/81193 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2225/06582 ,  H01L2924/01029 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: The present disclosure relates to a semiconductor device and a method for manufacturing the same. The semiconductor device includes a semiconductor die, a semiconductor element and a solder layer. The semiconductor die includes a copper pillar. The semiconductor element includes a surface finish layer, wherein the material of the surface finish layer is a combination of at least two of nickel, gold, and palladium. The solder layer is disposed between the copper pillar and the surface finish layer. The solder layer includes a first intermetallic compound (IMC) and a second IMC, wherein the first IMC includes a combination of at least two of copper, nickel and tin. The second IMC is a combination of gold and tin, a combination of palladium and tin, or both.

Abstract translation: 本公开涉及一种半导体器件及其制造方法。 半导体器件包括半导体管芯，半导体元件和焊料层。 半导体管芯包括铜柱。 半导体元件包括表面光洁度层，其中表面光洁度层的材料是镍，金和钯中的至少两种的组合。 焊料层设置在铜柱和表面光洁度层之间。 焊料层包括第一金属间化合物（IMC）和第二IMC，其中第一IMC包括铜，镍和锡中的至少两种的组合。 第二个IMC是金和锡的组合，钯和锡的组合，或两者兼而有之。

公开(公告)号：US09960136B2

公开(公告)日：2018-05-01

申请号：US15239745

申请日：2016-08-17

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yu-Hsiang Hsiao ,  Chiu-Wen Lee ,  Ping-Feng Yang ,  Kwang-Lung Lin

IPC: H01L23/00 ,  B23K1/00 ,  B23K35/26 ,  B23K35/30 ,  C22C9/02 ,  C22C13/00 ,  H01L25/065 ,  H01L25/00 ,  B23K101/40

CPC classification number: H01L24/13 ,  B23K1/0016 ,  B23K35/262 ,  B23K35/302 ,  B23K2101/40 ,  C22C9/02 ,  C22C13/00 ,  H01L24/05 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05147 ,  H01L2224/05572 ,  H01L2224/1182 ,  H01L2224/13025 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/13611 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/13686 ,  H01L2224/16146 ,  H01L2224/16503 ,  H01L2224/16507 ,  H01L2224/81193 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2225/06582 ,  H01L2924/01029 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A semiconductor device includes a first circuit layer, a copper pillar disposed adjacent to the first circuit layer, a second circuit layer and a solder layer. The second circuit layer includes an electrical contact and a surface finish layer disposed on the electrical contact, wherein a material of the surface finish layer is a combination of at least two of nickel, gold, and palladium. The solder layer is disposed between the copper pillar and the surface finish layer. The solder layer includes a first intermetallic compound (IMC) and a second IMC, wherein the first IMC includes a combination of two or more of copper, nickel and tin, and the second IMC includes a combination of gold and tin, a combination of palladium and tin, or both.