公开(公告)号：US20180158821A1

公开(公告)日：2018-06-07

申请号：US15370555

申请日：2016-12-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Changyong XIAO ,  Xusheng WU ,  Min-hwa CHI ,  Jie CHEN

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/823842 ,  H01L21/82385 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to gate structures with low resistance and methods of manufacture. The structure includes: an nFET device formed in a first cavity having a first volume which is filled with conductive material; and a pFET device forming in a second cavity having a second volume greater than the first volume. The second volume being filled with the conductive material.

公开(公告)号：US20150380409A1

公开(公告)日：2015-12-31

申请号：US14315885

申请日：2014-06-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mitsuhiro TOGO ,  Changyong XIAO ,  Yiqun LIU ,  Dina H. TRIYOSO ,  Rohit PAL

IPC: H01L27/092 ,  H01L21/321 ,  H01L21/265 ,  H01L21/8238 ,  H01L21/324

CPC classification number: H01L27/0922 ,  H01L21/26513 ,  H01L21/32115 ,  H01L21/324 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/845 ,  H01L27/0924 ,  H01L29/41791 ,  H01L29/49 ,  H01L29/4958 ,  H01L29/66545 ,  H01L29/66795

Abstract: A range of lowest, low and regular threshold voltages are provided to three p-type devices and three n-type devices co-fabricated on a same substrate. For the p-type devices, the range is achieved for the lowest using an additional thick layer of a p-type work function metal in a gate structure and oxidizing it, the low Vt is achieved with the thick p-type work function metal alone, and the regular Vt is achieved with a thinner layer of the p-type work function metal. For the n-type devices, the lowest Vt is achieved by implanting tantalum nitride with arsenic, argon, silicon or germanium and not adding any of the additional p-type work function metal in the gate structure, the low Vt is achieved by not adding the additional p-type work function metal, and the regular Vt is achieved with a thinnest layer of the p-type work function metal.

Abstract translation: 三个p型器件和在同一衬底上共同制造的三个n型器件提供了一个最低，低和规则阈值电压范围。 对于p型器件，使用栅极结构中的p型功函数金属的附加厚层并对其进行氧化来实现最低的范围，低Vt由厚的p型功函数金属单独实现 ，并且通过p型功函数金属的较薄层实现常规Vt。 对于n型器件，最低的Vt是通过用砷，氩，硅或锗注入氮化钽而不是在栅极结构中添加任何附加的p型功函数金属来实现的，低Vt是通过不添加 额外的p型功函数金属，而常规Vt是用最薄层的p型功函金属实现的。

公开(公告)号：US20150318351A1

公开(公告)日：2015-11-05

申请号：US14267541

申请日：2014-05-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng WU ,  Xiang HU ,  Changyong XIAO ,  Wanxun HE

IPC: H01L29/06 ,  H01L29/161 ,  H01L21/02 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/308 ,  H01L29/16 ,  H01L27/088

CPC classification number: H01L29/161 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/0259 ,  H01L21/02639 ,  H01L21/02664 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0657 ,  H01L29/7853

Abstract: A non-planar semiconductor structure includes raised semiconductor structures, e.g., fins, having epitaxial structures grown on top surfaces thereof, for example, epitaxial silicon naturally growing into a diamond shape. The surface area of the epitaxial structure may be increased by removing portion(s) thereof. The removal may create a multi-head (e.g., dual-head) epitaxial structure, together with the neck of the raised structure resembling a Y-shape. Raised structures that are not intended to include an epitaxial structure will be masked during epitaxial structure creation and modification. In addition, in order to have a uniform height, the filler material surrounding the raised structures is recessed around those to receive epitaxial structures.

Abstract translation: 非平面半导体结构包括凸起的半导体结构，例如具有在其顶表面上生长的外延结构的翅片，例如外延硅自然生长成菱形。 可以通过去除外延结构的部分来增加外延结构的表面积。 移除可以与类似于Y形的凸起结构的颈部一起形成多头（例如双头）外延结构。 在外延结构的制造和修改过程中，不会包含外延结构的凸起结构将被掩蔽。 此外，为了具有均匀的高度，围绕凸起结构的填充材料围绕接收外延结构的填充材料凹入。

公开(公告)号：US20160049400A1

公开(公告)日：2016-02-18

申请号：US14924486

申请日：2015-10-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mitsuhiro TOGO ,  Changyong XIAO ,  Yiqun LIU ,  Dina H. TRIYOSO ,  Rohit PAL

IPC: H01L27/092

CPC classification number: H01L27/0922 ,  H01L21/26513 ,  H01L21/32115 ,  H01L21/324 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/845 ,  H01L27/0924 ,  H01L29/41791 ,  H01L29/49 ,  H01L29/4958 ,  H01L29/66545 ,  H01L29/66795

Abstract: A range of lowest, low and regular threshold voltages are provided to three p-type devices and three n-type devices co-fabricated on a same substrate. For the p-type devices, the range is achieved for the lowest using an additional thick layer of a p-type work function metal in a gate structure and oxidizing it, the low Vt is achieved with the thick p-type work function metal alone, and the regular Vt is achieved with a thinner layer of the p-type work function metal. For the n-type devices, the lowest Vt is achieved by implanting tantalum nitride with arsenic, argon, silicon or germanium and not adding any of the additional p-type work function metal in the gate structure, the low Vt is achieved by not adding the additional p-type work function metal, and the regular Vt is achieved with a thinnest layer of the p-type work function metal.

公开(公告)号：US20140327139A1

公开(公告)日：2014-11-06

申请号：US13875377

申请日：2013-05-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jialin YU ,  Jilin XIA ,  Huang LIU ,  Wonwoo KIM ,  Changyong XIAO

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L23/5226 ,  H01L21/76846 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Contact structures and methods of fabricating contact structures of semiconductor devices are provided. One method includes, for instance: obtaining a substrate including a dielectric layer over the substrate; patterning the dielectric layer with at least one contact opening; providing a contact liner within the at least one contact opening in the dielectric layer; and filling the contact liner with a conductive material. In enhanced aspects, providing the contact liner within the at least one contact opening includes: depositing a first layer within the at least one contact opening in the dielectric layer; depositing a second layer over the first layer within the at least one contact opening; depositing at least one intermediate layer over the second layer within the at least one contact opening; and depositing a top layer over the at least one intermediate layer within the at least one contact opening.

Abstract translation: 提供了制造半导体器件的接触结构的接触结构和方法。 一种方法包括例如：在衬底上获得包括电介质层的衬底; 用至少一个接触开口构图介电层; 在所述电介质层中的所述至少一个接触开口内提供接触衬垫; 并用导电材料填充接触衬垫。 在增强的方面，在所述至少一个接触开口内提供所述接触衬垫包括：在所述电介质层中的所述至少一个接触开口内沉积第一层; 在所述至少一个接触开口内的第一层上沉积第二层; 在所述至少一个接触开口内沉积所述第二层上的至少一个中间层; 以及在所述至少一个接触开口内的所述至少一个中间层上沉积顶层。

公开(公告)号：US20160315084A1

公开(公告)日：2016-10-27

申请号：US14691960

申请日：2015-04-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xusheng WU ,  HongLiang SHEN ,  Changyong XIAO ,  Jianhua YIN ,  Jie CHEN ,  Jin Ping LIU ,  Hong YU ,  Zhenyu HU ,  Lan YANG ,  Wanxun HE

IPC: H01L27/092 ,  H01L29/10 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/82385 ,  H01L29/1033

Abstract: There is set forth herein in one embodiment a semiconductor structure having a first region and a second region. The first region can include fins of a first fin height and the second region can include fins of a second fin height.

Abstract translation: 这里在一个实施例中阐述了具有第一区域和第二区域的半导体结构。 第一区域可以包括第一翅片高度的翅片，并且第二区域可以包括具有第二翅片高度的翅片。

公开(公告)号：US20160155799A1

公开(公告)日：2016-06-02

申请号：US15002000

申请日：2016-01-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng WU ,  Changyong XIAO ,  Xiang HU ,  Wanxun HE

IPC: H01L29/06 ,  H01L29/20 ,  H01L29/161 ,  H01L27/092 ,  H01L29/16

CPC classification number: H01L29/0657 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02546 ,  H01L21/0259 ,  H01L21/02639 ,  H01L21/02664 ,  H01L21/30604 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0692 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L29/201

Abstract: A non-planar semiconductor structure includes mixed n-and-p type raised semiconductor structures, e.g., fins, having epitaxial structures grown on top surfaces thereof, for example, epitaxial silicon and silicon germanium, naturally growing into a diamond shape. The surface area of the epitaxial structures is increased by removing portion(s) thereof, masking each type as the other type is grown and then subsequently modified by the removal. The removal may create multi-head (e.g., dual-head) epitaxial structures, together with the neck of the respective raised structure resembling a Y-shape.

Abstract translation: 非平面半导体结构包括混合的n型和p型凸起半导体结构，例如具有在其顶表面上生长的外延结构的散热片，例如外延硅和硅锗，天然生长成菱形。 外延结构的表面积通过去除其部分而增加，当另一种类型生长然后随后通过去除而修饰时，掩蔽每种类型。 移除可以与类似于Y形的相应凸起结构的颈部一起产生多头（例如，双头）外延结构。

公开(公告)号：US20160126336A1

公开(公告)日：2016-05-05

申请号：US14527250

申请日：2014-10-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng WU ,  Changyong XIAO ,  Min-hwa CHI

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/423 ,  H01L21/311 ,  H01L29/417

CPC classification number: H01L29/66515 ,  H01L29/41775 ,  H01L29/42356 ,  H01L29/6653 ,  H01L29/66545

Abstract: Processes for forming merged CA/CB constructs and the resulting devices are disclosed. Embodiments include providing a replacement metal gate (RMG) between first and second sidewall spacers surrounded by an insulator on a substrate, the RMG having a dielectric layer directly on the first and second sidewall spacers and having metal on the dielectric layer; providing an oxide layer over the insulator, the first and second sidewall spacers, and the RMG; forming a source/drain contact hole through the oxide layer and the insulator, adjacent to the first sidewall spacer; forming a gate contact hole through the oxide layer over the source/drain contact hole and extending to the metal of the RMG; enlarging the source/drain contact hole to the metal of the RMG; and filling the enlarged source/drain contact hole and gate contact hole with metal.

Abstract translation: 公开了形成合并的CA / CB结构和所得到的设备的过程。 实施例包括在由衬底上的绝缘体围绕的第一和第二侧壁间隔之间提供置换金属栅极（RMG），RMG直接在第一和第二侧壁间隔物上并且在电介质层上具有金属; 在绝缘体上方提供氧化物层，第一和第二侧壁间隔物以及RMG; 形成与所述第一侧壁间隔物相邻的所述氧化物层和所述绝缘体的源极/漏极接触孔; 在源极/漏极接触孔上形成通过氧化物层的栅极接触孔并延伸到RMG的金属; 将源极/漏极接触孔扩大到RMG的金属; 并用金属填充放大的源极/漏极接触孔和栅极接触孔。

公开(公告)号：US20150332963A1

公开(公告)日：2015-11-19

申请号：US14281454

申请日：2014-05-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng WU ,  Changyong XIAO ,  Min-hwa CHI

IPC: H01L21/768

CPC classification number: H01L21/76879 ,  H01L21/28518 ,  H01L21/76804 ,  H01L21/76816 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/485 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A transistor, planar or non-planar (e.g., FinFET), includes T-shaped contacts to the source, drain and gate. The top portion of the T-shaped contact is wider than the bottom portion, the bottom portion complying with design rule limits. A conductor-material filled trench through a multi-layer etching stack above the transistor provides the top portions of the T-shaped contacts. Tapered spacers along inner sidewalls of the top contact portion prior to filling allow for etching a narrower bottom trench down to the gate, and to the source/drain for silicidation prior to filling.

Abstract translation: 晶体管，平面或非平面（例如，FinFET）包括到源极，漏极和栅极的T形接触。 T形接触件的顶部比底部宽，底部符合设计规则限制。 通过晶体管上方的多层蚀刻堆叠的导体材料填充沟槽提供了T形触头的顶部。 在填充之前，顶部接触部分的内侧壁上的锥形间隔物允许在填充之前将较窄的底部沟槽蚀刻到栅极和源极/漏极以进行硅化。

公开(公告)号：US20150318217A1

公开(公告)日：2015-11-05

申请号：US14267611

申请日：2014-05-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xusheng WU ,  Xiang HU ,  Changyong XIAO ,  Wanxun HE

IPC: H01L21/8238 ,  H01L21/02 ,  H01L29/201 ,  H01L29/161 ,  H01L29/16 ,  H01L21/306 ,  H01L27/092

CPC classification number: H01L29/0657 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02546 ,  H01L21/0259 ,  H01L21/02639 ,  H01L21/02664 ,  H01L21/30604 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0692 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L29/201

Abstract: A non-planar semiconductor structure includes mixed n-and-p type raised semiconductor structures, e.g., fins, having epitaxial structures grown on top surfaces thereof, for example, epitaxial silicon and silicon germanium, naturally growing into a diamond shape. The surface area of the epitaxial structures is increased by removing portion(s) thereof, masking each type as the other type is grown and then subsequently modified by the removal. The removal may create multi-head (e.g., dual-head) epitaxial structures, together with the neck of the respective raised structure resembling a Y-shape.

Abstract translation: 非平面半导体结构包括混合的n型和p型凸起半导体结构，例如具有在其顶表面上生长的外延结构的散热片，例如外延硅和硅锗，天然生长成菱形。 外延结构的表面积通过去除其部分而增加，当另一种类型生长然后随后通过去除而修饰时，掩蔽每种类型。 移除可以与类似于Y形的相应凸起结构的颈部一起产生多头（例如，双头）外延结构。