公开(公告)号：US09589848B2

公开(公告)日：2017-03-07

申请号：US14678024

申请日：2015-04-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Ghavam G. Shahidi

IPC: H01L21/027 ,  H01L21/205 ,  H01L21/308 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/02 ,  H01L21/20 ,  H01L21/033 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L21/3065 ,  H01L29/16

CPC classification number: H01L21/823807 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/033 ,  H01L21/2018 ,  H01L21/2053 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/16 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7855

Abstract: Silicon and silicon germanium fins are formed on a semiconductor wafer or other substrate in a manner that facilitates production of closely spaced nFET and pFET devices. A patterned mandrel layer is employed for forming one or more recesses in the wafer prior to the epitaxial growth of a silicon germanium layer that fills the recess. Spacers are formed on the side walls of the patterned mandrel layer followed by removal of the mandrel layer. The exposed areas of the wafer and silicon germanium layer between the spacers are etched to form fins usable for nFET devices from the wafer and fins usable for pFET devices from the silicon germanium layer.

Abstract translation: 在半导体晶片或其它基板上形成硅和硅锗翅片，以便于产生紧密间隔的nFET和pFET器件。 在形成填充凹部的硅锗层的外延生长之前，使用图案化心轴层在晶片中形成一个或多个凹槽。 间隔件形成在图案化心轴层的侧壁上，随后移除心轴层。 蚀刻在间隔物之间​​的晶片和硅锗层的暴露区域以形成可用于来自晶片的nFET器件的鳍片和可用于来自硅锗层的pFET器件的鳍片。

公开(公告)号：US09577065B2

公开(公告)日：2017-02-21

申请号：US14707923

申请日：2015-05-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Wilfried E. Haensch ,  Bahman Hekmatshoar-Tabari ,  Ali Khakifirooz ,  Tak H. Ning ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC: H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/786 ,  H01L21/02 ,  H01L21/225 ,  H01L29/417 ,  H01L21/265 ,  H01L29/08

CPC classification number: H01L29/66477 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/2257 ,  H01L21/265 ,  H01L21/823814 ,  H01L21/84 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/41783 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/7834 ,  H01L29/7841 ,  H01L29/78618 ,  H01L29/78621

Abstract: A back end of line device and method for fabricating a transistor device include a substrate having an insulating layer formed thereon and a channel layer formed on the insulating layer. A gate structure is formed on the channel layer. Dopants are implanted into an upper portion of the channel layer on opposite sides of the gate structure to form shallow source and drain regions using a low temperature implantation process. An epitaxial layer is selectively grown on the shallow source and drain regions to form raised regions above the channel layer and against the gate structure using a low temperature plasma enhanced chemical vapor deposition process, wherein low temperature is less than about 400 degrees Celsius.

Abstract translation: 用于制造晶体管器件的线路器件的后端和方法包括其上形成有绝缘层的衬底和形成在绝缘层上的沟道层。 栅极结构形成在沟道层上。 在栅极结构的相对侧将掺杂剂注入沟道层的上部，以使用低温注入工艺形成浅的源极和漏极区。 在浅源极和漏极区上选择性地生长外延层，以使用低温等离子体增强化学气相沉积工艺在通道层上方和栅极结构上形成凸起区域，其中低温小于约400摄氏度。

公开(公告)号：US09391180B2

公开(公告)日：2016-07-12

申请号：US14725755

申请日：2015-05-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bahman Hekmatshoar-Tabari ,  Tak H. Ning ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC: H01L29/66 ,  H01L29/737 ,  H01L21/02 ,  H01L29/735 ,  H01L29/16 ,  H01L29/165 ,  H01L21/265 ,  H01L21/30 ,  H01L29/08 ,  H01L29/10 ,  H01L29/36 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L29/737 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02507 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/0262 ,  H01L21/265 ,  H01L21/3003 ,  H01L29/0817 ,  H01L29/1004 ,  H01L29/1604 ,  H01L29/165 ,  H01L29/36 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/66242 ,  H01L29/735

Abstract: Heterojunction bipolar transistors are provided that include at least one contact (e.g., collector, emitter, and/or base) formed by a heterojunction between a crystalline semiconductor material and a doped non-crystalline semiconductor material layer. An interfacial intrinsic non-crystalline semiconductor material layer is present at the heterojunction between the crystalline semiconductor material and the doped non-crystalline semiconductor material layer. The presence of the interfacial intrinsic non-crystalline semiconductor material layer improves the surface passivation of the crystalline semiconductor material by reducing the interface defect density at the heterojunction.

公开(公告)号：US09484430B2

公开(公告)日：2016-11-01

申请号：US14720328

申请日：2015-05-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Wilfried E. Haensch ,  Bahman Hekmatshoar-Tabari ,  Ali Khakifirooz ,  Tak H. Ning ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC: H01L21/84 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/786 ,  H01L21/02 ,  H01L21/225 ,  H01L29/40 ,  H01L29/417 ,  H01L21/265 ,  H01L29/08

CPC classification number: H01L29/66477 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/2257 ,  H01L21/265 ,  H01L21/823814 ,  H01L21/84 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/41783 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/7834 ,  H01L29/7841 ,  H01L29/78618 ,  H01L29/78621

Abstract: A back end of line device and method for fabricating a transistor device include a substrate having an insulating layer formed thereon and a channel layer formed on the insulating layer. A gate structure is formed on the channel layer. Dopants are implanted into an upper portion of the channel layer on opposite sides of the gate structure to form shallow source and drain regions using a low temperature implantation process. An epitaxial layer is selectively grown on the shallow source and drain regions to form raised regions above the channel layer and against the gate structure using a low temperature plasma enhanced chemical vapor deposition process, wherein low temperature is less than about 400 degrees Celsius.

公开(公告)号：US09466651B2

公开(公告)日：2016-10-11

申请号：US14966161

申请日：2015-12-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Stephen W. Bedell, III ,  Bahman Hekmatshoartabari ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC: H01L27/32 ,  H01L27/12 ,  H01L51/52

CPC classification number: H01L27/3262 ,  H01L21/7624 ,  H01L21/76254 ,  H01L27/1218 ,  H01L27/1262 ,  H01L27/1266 ,  H01L27/3248 ,  H01L51/5218 ,  H01L51/5221 ,  H01L51/5237 ,  H01L2227/323 ,  H01L2227/326 ,  H01L2251/5338

Abstract: High resolution active matrix structures are fabricated using techniques applicable to flexible substrates. A backplane layer including active semiconductor devices is formed using a semiconductor-on-insulator substrate. The substrate is thinned using a layer transfer technique or chemical/mechanical processing. Driver transistors are formed on the semiconductor layer of the substrate along with additional circuits that provide other functions such as computing or sensing. Contacts to passive devices such as organic light emitting diodes may be provided by heavily doped regions formed in the handle layer of the substrate and then isolated. A gate dielectric layer may be formed on the semiconductor layer, which functions as a channel layer, or the insulator layer of the substrate may be employed as a gate dielectric layer.

公开(公告)号：US20160099297A1

公开(公告)日：2016-04-07

申请号：US14966161

申请日：2015-12-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Stephen W. Bedell, III ,  Bahman Hekmatshoartabari ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC: H01L27/32 ,  H01L51/52 ,  H01L27/12

CPC classification number: H01L27/3262 ,  H01L21/7624 ,  H01L21/76254 ,  H01L27/1218 ,  H01L27/1262 ,  H01L27/1266 ,  H01L27/3248 ,  H01L51/5218 ,  H01L51/5221 ,  H01L51/5237 ,  H01L2227/323 ,  H01L2227/326 ,  H01L2251/5338

Abstract: High resolution active matrix structures are fabricated using techniques applicable to flexible substrates. A backplane layer including active semiconductor devices is formed using a semiconductor-on-insulator substrate. The substrate is thinned using a layer transfer technique or chemical/mechanical processing. Driver transistors are formed on the semiconductor layer of the substrate along with additional circuits that provide other functions such as computing or sensing. Contacts to passive devices such as organic light emitting diodes may be provided by heavily doped regions formed in the handle layer of the substrate and then isolated. A gate dielectric layer may be formed on the semiconductor layer, which functions as a channel layer, or the insulator layer of the substrate may be employed as a gate dielectric layer.

公开(公告)号：US09478651B2

公开(公告)日：2016-10-25

申请号：US14732680

申请日：2015-06-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stephen W. Bedell ,  Bahman Hekmatshoartabari ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC: H01L29/06 ,  H01L29/778 ,  H01L27/088 ,  H01L21/8252 ,  H01L27/06 ,  H01L27/095 ,  H01L29/872 ,  H01L29/205 ,  H01L29/66 ,  H01L21/683 ,  G06F17/50 ,  H01L29/20 ,  H01L29/40

CPC classification number: H01L29/7786 ,  G06F17/5045 ,  G06F17/5063 ,  H01L21/6835 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/088 ,  H01L27/095 ,  H01L29/0634 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/66462 ,  H01L29/872 ,  H01L2221/68363

Abstract: A circuit includes a first field effect transistor having a gate, a first drain-source terminal, and a second drain-source terminal; and a second field effect transistor having a gate, a first drain-source terminal, and a second drain-source terminal. The second field effect transistor and the first field effect transistor are of the same type, i.e., both re-channel transistors or both p-channel transistors. The second drain-source terminal of the first field effect transistor is coupled to the first drain-source terminal of the second field effect transistor; and the gate of the second field effect transistor is coupled to the first drain-source terminal of the second field effect transistor. The resulting three-terminal device can be substituted for a single field effect transistor that would otherwise suffer breakdown under proposed operating conditions.

Abstract translation: 电路包括具有栅极的第一场效应晶体管，第一漏极 - 源极端子和第二漏极 - 源极端子; 以及具有栅极的第二场效应晶体管，第一漏极 - 源极端子和第二漏极 - 源极端子。 第二场效应晶体管和第一场效应晶体管是相同类型的，即重新沟道晶体管或两个p沟道晶体管。 第一场效应晶体管的第二漏极 - 源极端子耦合到第二场效应晶体管的第一漏极 - 源极端子; 并且第二场效应晶体管的栅极耦合到第二场效应晶体管的第一漏极 - 源极端子。 所得到的三端子器件可以替代否则在所提出的工作条件下会损坏的单个场效应晶体管。

公开(公告)号：US09472607B2

公开(公告)日：2016-10-18

申请号：US14717344

申请日：2015-05-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bahman Hekmatshoartabari ,  Tak H. Ning ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC: H01L27/32 ,  H01L23/522 ,  H01L27/06 ,  H01L27/12 ,  H01L29/04 ,  H01L29/10 ,  H01L29/16 ,  H01L29/73 ,  H01L29/808 ,  G09G3/32

CPC classification number: H01L27/3276 ,  G09G3/3225 ,  G09G2300/0842 ,  H01L23/5226 ,  H01L27/0694 ,  H01L27/1207 ,  H01L27/3244 ,  H01L27/326 ,  H01L27/3265 ,  H01L29/04 ,  H01L29/1004 ,  H01L29/16 ,  H01L29/73 ,  H01L29/808 ,  H01L2251/5315 ,  H01L2251/533 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A hybrid integrated circuit device includes a semiconductor-on-insulator substrate having a base substrate, a semiconductor layer and a dielectric layer disposed therebetween, the base substrate being reduced in thickness. First devices are formed in the semiconductor layer, the first devices being connected to first metallizations on a first side of the dielectric layer. Second devices are formed in the base substrate, the second devices being connected to second metallizations formed on a second side of the dielectric layer opposite the first side. A through via connection is configured to connect the first metallizations to the second metallizations through the dielectric layer. Pixel circuits and methods are also disclosed.

公开(公告)号：US09406717B2

公开(公告)日：2016-08-02

申请号：US14725151

申请日：2015-05-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Stephen W. Bedell ,  Bahman Hekmatshoartabari ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC: H01L27/146

CPC classification number: H01L27/14692 ,  H01L27/1461 ,  H01L27/1462 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14645 ,  H01L27/14687

Abstract: A method for forming a back-illuminated image sensor includes forming a higher doped crystalline layer on a crystalline substrate, growing a lower doped crystalline layer on the higher doped crystalline layer and forming a photodiode and component circuitry from the lower doped crystalline layer. Metallization structures are formed to make connections to and between components. The crystalline substrate is removed to expose the higher doped crystalline layer. An optical component structure is provided on an exposed surface of the higher doped crystalline layer to receive light therein such that the higher doped crystalline layer provides a passivation layer for the photodiode and the component circuitry.

公开(公告)号：US09373691B2

公开(公告)日：2016-06-21

申请号：US13961282

申请日：2013-08-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bahman Hekmatshoartabari ,  Ali Khakifirooz ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC: H01L29/66 ,  H01L29/40 ,  H01L29/49 ,  H01L29/51 ,  H01L21/04 ,  H01L29/78 ,  H01L29/16 ,  H01L21/762

CPC classification number: H01L29/66068 ,  H01L21/049 ,  H01L21/76254 ,  H01L29/1608 ,  H01L29/401 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/518 ,  H01L29/78

Abstract: A method for forming a semiconductor device includes forming a dielectric layer on a first substrate and wafer bonding the dielectric layer of the first substrate to a second substrate including SiC with a passivating layer formed on the SiC. A portion of the first substrate is removed from a side opposite the dielectric layer. The dielectric layer is patterned to form a gate dielectric for a field effect transistor formed on the second substrate.

Abstract translation: 一种形成半导体器件的方法包括在第一衬底上形成电介质层，并将第一衬底的电介质层与包含SiC的第二衬底相结合，并在SiC上形成钝化层。 从与电介质层相对的一侧去除第一衬底的一部分。 对电介质层进行构图以形成用于形成在第二衬底上的场效应晶体管的栅极电介质。