公开(公告)号：US10361281B2

公开(公告)日：2019-07-23

申请号：US15911892

申请日：2018-03-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Takashi Ando ,  Eduard A. Cartier ,  Kisik Choi ,  Vijay Narayanan

IPC: H01L21/02 ,  H01L21/28 ,  H01L29/66 ,  H01L21/321 ,  H01L21/324 ,  H01L29/423 ,  H01L21/3205

Abstract: A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; performing a first rapid thermal anneal; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill.

公开(公告)号：US20180197972A1

公开(公告)日：2018-07-12

申请号：US15911892

申请日：2018-03-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Takashi Ando ,  Eduard A. Cartier ,  Kisik Choi ,  Vijay Narayanan

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/324 ,  H01L21/28 ,  H01L29/423 ,  H01L21/321

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/28017 ,  H01L21/28088 ,  H01L21/32055 ,  H01L21/321 ,  H01L21/324 ,  H01L29/4232 ,  H01L29/66 ,  H01L29/66545 ,  H01L29/6681

Abstract: A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; performing a first rapid thermal anneal; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill.

公开(公告)号：US09960252B2

公开(公告)日：2018-05-01

申请号：US15258597

申请日：2016-09-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Takashi Ando ,  Eduard A. Cartier ,  Kisik Choi ,  Vijay Narayanan

IPC: H01L21/3205 ,  H01L29/66 ,  H01L21/28 ,  H01L21/324 ,  H01L29/423 ,  H01L21/321 ,  H01L21/02

CPC classification number: H01L29/66545 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/28017 ,  H01L21/28088 ,  H01L21/32055 ,  H01L21/321 ,  H01L21/324 ,  H01L29/4232 ,  H01L29/66 ,  H01L29/66795 ,  H01L29/6681

Abstract: A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; performing a first rapid thermal anneal; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill.

公开(公告)号：US09748145B1

公开(公告)日：2017-08-29

申请号：US15055826

申请日：2016-02-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Balaji Kannan ,  Unoh Kwon ,  Siddarth Krishnan ,  Takashi Ando ,  Vijay Narayanan

IPC: H01L21/8238 ,  H01L21/324 ,  H01L21/225 ,  H01L29/66 ,  H01L27/092

CPC classification number: H01L29/66545 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518

Abstract: Semiconductor device fabrication methods are provided which include: providing a structure with at least one region and including a dielectric layer disposed over a substrate; forming a multilayer stack structure including a threshold-voltage adjusting layer over the dielectric layer, the multilayer stack structure including a first threshold-voltage adjusting layer in a first region of the at least one region, and a second threshold-voltage adjusting layer in a second region of the at least one region; and annealing the structure to define a varying threshold voltage of the at least one region, the annealing facilitating diffusion of at least one threshold voltage adjusting species from the first threshold-voltage adjusting layer and the second threshold-voltage adjusting layer into the dielectric layer, where a threshold voltage of the first region is independent of the threshold voltage of the second region.

公开(公告)号：US09660027B2

公开(公告)日：2017-05-23

申请号：US14887572

申请日：2015-10-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Siddarth A. Krishnan ,  Unoh Kwon ,  Vijay Narayanan ,  Jeffrey W. Sleight

IPC: H01L29/06 ,  H01L29/41 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L29/0673 ,  H01L29/083 ,  H01L29/165 ,  H01L29/205 ,  H01L29/41758 ,  H01L29/42356 ,  H01L29/45 ,  H01L29/458 ,  H01L29/66356 ,  H01L29/66469 ,  H01L29/66553 ,  H01L29/7391 ,  H01L29/775

Abstract: After forming a buried nanowire segment surrounded by a gate structure located on a substrate, an epitaxial source region is grown on a first end of the buried nanowire segment while covering a second end of the buried nanowire segment and the gate structure followed by growing an epitaxial drain region on the second end of the buried nanowire segment while covering the epitaxial source region and the gate structure. The epitaxial source region includes a first semiconductor material and dopants of a first conductivity type, while the epitaxial drain region includes a first semiconductor material different from the first semiconductor material and dopants of a second conductivity type opposite the first conductivity type.

公开(公告)号：US09564505B2

公开(公告)日：2017-02-07

申请号：US14254939

申请日：2014-04-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Michael P. Chudzik ,  Martin M. Frank ,  Herbert L. Ho ,  Mark J. Hurley ,  Rashmi Jha ,  Naim Moumen ,  Vijay Narayanan ,  Dae-Gyu Park ,  Vamsi K. Paruchuri

IPC: H01L21/70 ,  H01L29/49 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/51

CPC classification number: H01L29/49 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/4958 ,  H01L29/517

Abstract: Ion implantation to change an effective work function for dual work function metal gate integration is presented. One method may include forming a high dielectric constant (high-k) layer over a first-type field effect transistor (FET) region and a second-type FET region; forming a metal layer having a first effective work function compatible for a first-type FET over the first-type FET region and the second-type FET region; and changing the first effective work function to a second, different effective work function over the second-type FET region by implanting a species into the metal layer over the second-type FET region.

Abstract translation: 提出了离子注入来改变双功能金属栅极整合的有效功函数。 一种方法可以包括在第一类型场效应晶体管（FET）区域和第二类型FET区域上形成高介电常数（高k）层; 在第一型FET区域和第二类型FET区域上形成具有与第一型FET兼容的第一有效功函数的金属层; 以及通过在第二类型FET区域上将金属注入到金属层中，将第一有效功函数改变为第二类不同的有效功函数。

公开(公告)号：US09397175B2

公开(公告)日：2016-07-19

申请号：US14881766

申请日：2015-10-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Emre Alptekin ,  Unoh Kwon ,  Wing L. Lai ,  Zhengwen Li ,  Vijay Narayanan ,  Ravikumar Ramachandran ,  Reinaldo A. Vega

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/40 ,  H01L29/51 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/49

CPC classification number: H01L29/408 ,  H01L21/82345 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659

Abstract: A first gate structure and a second gate structure are formed over a semiconductor material layer. The first gate structure includes a planar silicon-based gate dielectric, a planar high-k gate dielectric, a metallic nitride portion, and a first semiconductor material portion, and the second gate structure includes a silicon-based dielectric material portion and a second semiconductor material portion. After formation of gate spacers and a planarization dielectric layer, the second gate structure is replaced with a transient gate structure including a chemical oxide portion and a second high-k gate dielectric. A work-function metal layer and a conductive material portion can be formed in each gate electrode by replacement of semiconductor material portions. A gate electrode includes the planar silicon-based gate dielectric, the planar high-k gate dielectric, and a U-shaped high-k gate dielectric, and another gate electrode includes the chemical oxide portion and another U-shaped high-k gate dielectric.

Abstract translation: 在半导体材料层上形成第一栅极结构和第二栅极结构。 第一栅极结构包括平面硅基栅极电介质，平面高k栅极电介质，金属氮化物部分和第一半导体材料部分，并且第二栅极结构包括硅基电介质材料部分和第二半导体 材料部分。 在形成栅极间隔物和平坦化介电层之后，用包括化学氧化物部分和第二高k栅极电介质的瞬态栅极结构来代替第二栅极结构。 可以通过更换半导体材料部分在每个栅电极中形成功函数金属层和导电材料部分。 栅电极包括平面硅基栅极电介质，平面高k栅极电介质和U形高k栅极电介质，另一个栅电极包括化学氧化物部分和另一个U形高k栅极电介质 。

公开(公告)号：US20150243762A1

公开(公告)日：2015-08-27

申请号：US14699843

申请日：2015-04-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Takashi Ando ,  Eduard A. Cartier ,  Kisik Choi ,  Vijay Narayanan

IPC: H01L29/66 ,  H01L21/321 ,  H01L21/28

CPC classification number: H01L29/66545 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/28017 ,  H01L21/28088 ,  H01L21/32055 ,  H01L21/321 ,  H01L21/324 ,  H01L29/4232 ,  H01L29/66 ,  H01L29/66795 ,  H01L29/6681

Abstract: A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; performing a first rapid thermal anneal; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill.

公开(公告)号：US09960233B2

公开(公告)日：2018-05-01

申请号：US15600837

申请日：2017-05-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Siddarth A. Krishnan ,  Unoh Kwon ,  Vijay Narayanan ,  Jeffrey W. Sleight

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/739 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/45 ,  H01L29/165 ,  H01L29/205

CPC classification number: H01L29/0673 ,  H01L29/083 ,  H01L29/165 ,  H01L29/205 ,  H01L29/41758 ,  H01L29/42356 ,  H01L29/45 ,  H01L29/458 ,  H01L29/66356 ,  H01L29/66469 ,  H01L29/66553 ,  H01L29/7391 ,  H01L29/775

Abstract: After forming a buried nanowire segment surrounded by a gate structure located on a substrate, an epitaxial source region is grown on a first end of the buried nanowire segment while covering a second end of the buried nanowire segment and the gate structure followed by growing an epitaxial drain region on the second end of the buried nanowire segment while covering the epitaxial source region and the gate structure. The epitaxial source region includes a first semiconductor material and dopants of a first conductivity type, while the epitaxial drain region includes a first semiconductor material different from the first semiconductor material and dopants of a second conductivity type opposite the first conductivity type.

公开(公告)号：US20160308025A1

公开(公告)日：2016-10-20

申请号：US14685944

申请日：2015-04-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Michael P. Chudzik ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Vijay Narayanan ,  Jeffrey W. Sleight

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/20 ,  H01L29/88 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/02538 ,  H01L21/02617 ,  H01L29/0657 ,  H01L29/20 ,  H01L29/267 ,  H01L29/66151 ,  H01L29/66356 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7391 ,  H01L29/785 ,  H01L29/88

Abstract: A semiconductor structure includes a substrate and an intrinsic replacement channel. A tunneling field effect transistor (TFET) fin may be formed by the intrinsic replacement channel, a p-fin and an n-fin formed upon the substrate. The p-fin may serve as the source of the TFET and the n-fin may serve as the drain of the TFET. The replacement channel may be formed in place of a sacrificial channel of a diode fin that includes the p-fin, the n-fin, and the sacrificial channel at the p-fin and n-fin junction.

Abstract translation: 半导体结构包括衬底和固有置换通道。 隧道场效应晶体管（TFET）鳍可以由本征替换沟道，形成在衬底上的p鳍和n鳍形成。 p鳍可以用作TFET的源极，并且n鳍可以用作TFET的漏极。 可以形成替代通道来代替在p鳍和n鳍结上包括p鳍，n鳍和牺牲沟道的二极管鳍片的牺牲通道。