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    SEMICONDUCTOR JUNCTION FORMATION
    1.
    发明申请
    SEMICONDUCTOR JUNCTION FORMATION 有权
    半导体结形成

    公开(公告)号：US20160133727A1

    公开(公告)日：2016-05-12

    申请号：US14537832

    申请日：2014-11-10

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Pouya Hashemi ,  Shogo Mochizuki ,  Alexander Reznicek ,  Dominic J. Schepis

    IPC: H01L29/66 ,  H01L29/417 ,  H01L29/08 ,  H01L29/78 ,  H01L29/06

    CPC classification number: H01L29/66795 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/7851

    Abstract: A semiconductor structure, such as a FinFET, etc., includes a bi-portioned junction. The bi-portioned junction includes a doped outer portion and a doped inner portion. The dopant concentration of the outer portion is less than the dopant concentration of the inner portion. An electrical connection is formed by diffusion of the dopants within outer portion into a channel region and diffusion of the dopants within the outer portion into the inner region. A low contact resistance is achieved by a contact electrically contacting the relatively higher doped inner portion while device shorting is limited by the relatively lower doped outer portion.

    Abstract translation: 诸如FinFET等的半导体结构包括双分支结。 双分支结包括掺杂的外部部分和掺杂的内部部分。 外部部分的掺杂剂浓度小于内部部分的掺杂剂浓度。 通过将外部部分内的掺杂剂扩散到沟道区域中并且将外部部分内的掺杂剂扩散到内部区域中来形成电连接。 低接触电阻通过电接触相对较高的掺杂内部部分的接触来实现，同时器件短路由相对较低的掺杂外部部分限制。

    Semiconductor structure with aspect ratio trapping capabilities
    2.
    发明授权
    Semiconductor structure with aspect ratio trapping capabilities 有权
    具有纵横比捕获能力的半导体结构

    公开(公告)号：US09330908B2

    公开(公告)日：2016-05-03

    申请号：US13925911

    申请日：2013-06-25

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Pouya Hashemi ,  Ali Khakifirooz ,  Alexander Reznicek

    IPC: H01L21/02 ,  H01L21/8258 ,  H01L21/8238 ,  H01L27/088

    CPC classification number: H01L21/02538 ,  H01L21/02373 ,  H01L21/02441 ,  H01L21/02447 ,  H01L21/02494 ,  H01L21/823807 ,  H01L21/8258 ,  H01L27/088

    Abstract: A semiconductor structure includes a first semiconductor region. The first semiconductor region includes a first semiconductor layer composed of a group IV semiconductor material having a top surface and a back surface. The first semiconductor layer has an opening in the top surface to at least a depth greater than an aspect ratio trapping (ART) distance. The first semiconductor region also has a second semiconductor layer composed of a group III/V semiconductor compound deposited within the opening and on the top surface of the first semiconductor layer. The second semiconductor layer forms an ART region from the bottom of the opening to the ART distance.

    Abstract translation: 半导体结构包括第一半导体区域。 第一半导体区域包括由具有顶表面和后表面的IV族半导体材料组成的第一半导体层。 第一半导体层在顶表面具有至少大于纵横比捕获（ART）距离的深度的开口。 第一半导体区域还具有由沉积在第一半导体层的开口内和顶表面上的III / V族半导体化合物构成的第二半导体层。 第二半导体层从开口的底部到ART距离形成ART区域。

    Uniform depth fin trench formation
    4.
    发明授权
    Uniform depth fin trench formation 有权
    均匀深度鳍状沟形成

    公开(公告)号：US09472460B1

    公开(公告)日：2016-10-18

    申请号：US15007494

    申请日：2016-01-27

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Alexander Reznicek ,  Kangguo Cheng ,  Ali Khakifirooz ,  Dominic J. Schepis ,  Pouya Hashemi

    IPC: H01L21/8234 ,  H01L29/06 ,  H01L21/228 ,  H01L21/3065 ,  H01L21/02

    CPC classification number: H01L21/823431 ,  H01L21/3065 ,  H01L29/785

    Abstract: Methods for forming substantially uniform depth trenches and/or semiconductor fins from the trenches are disclosed. Embodiments of the method may include depositing a germanium including layer over a substrate, the substrate including a plurality of sacrificial semiconductor fins, each pair of sacrificial semiconductor fins separated by a sacrificial pillar. Germanium is diffused from the germanium including layer into the plurality of sacrificial semiconductor fins to a defined uniform depth. The germanium including layer is removed, and the plurality of sacrificial semiconductor fins are etched to the defined uniform depth and selective to the substrate, creating a plurality of trenches having a substantially uniform depth. The trenches can be used to epitaxial grow semiconductor fins having substantially uniform height.

    Abstract translation: 公开了从沟槽形成基本均匀的深度沟槽和/或半导体鳍片的方法。 该方法的实施例可以包括在衬底上沉积包含锗的层，衬底包括多个牺牲半导体鳍片，每对牺牲半导体鳍片由牺牲柱分隔开。 锗从含锗层扩散到多个牺牲半导体鳍片到规定的均匀深度。 去除含锗层，并且将多个牺牲半导体散热片蚀刻到规定的均匀深度并对衬底有选择性，从而产生具有基本均匀深度的多个沟槽。 沟槽可用于外延生长具有基本均匀的高度的半导体鳍片。

    INTEGRATED STRAINED FIN AND RELAXED FIN
    6.
    发明申请
    INTEGRATED STRAINED FIN AND RELAXED FIN 审中-公开
    集成应变熔融和放松的FIN

    公开(公告)号：US20160268378A1

    公开(公告)日：2016-09-15

    申请号：US14645477

    申请日：2015-03-12

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Pouya Hashemi ,  Ali Khakifirooz ,  Alexander Reznicek ,  Dominic J. Schepis

    IPC: H01L29/10 ,  H01L29/16 ,  H01L29/66 ,  H01L29/36 ,  H01L27/092 ,  H01L21/8234

    CPC classification number: H01L29/1054 ,  H01L21/18 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/161

    Abstract: A relaxed fin and a strained fin are formed upon a semiconductor substrate. The strained fin is more highly strained relative to relaxed fin. In a particular example, the relaxed fin may be SiGe (e.g., between 20% atomic Ge concentration and 40% atomic Ge concentration, etc.) and strained fin may be SiGe (e.g., between 50% atomic Ge concentration and 80% atomic Ge concentration, etc.). The strained fin may be located in a pFET region and the relaxed fin may be located in an nFET region of a semiconductor device. As such, mobility benefits may be achieved with the strained fin in the pFET region whilst mobility liabilities may be limited with the relaxed fin in nFET region. The height of the strained fin is greater relative to a critical thickness that which growth defects occur in an epitaxially formed Si blanket layer or in an epitaxially formed Ge blanket layer.

    Abstract translation: 在半导体基板上形成松弛的翅片和应变翅片。 相对于松散的翅片，应变翅片更加紧张。 在特定的例子中，松散翅片可以是SiGe（例如，在20％的原子Ge浓度和40％的原子Ge浓度之间等等），并且应变翅片可以是SiGe（例如，在50％的原子Ge浓度和80％的原子Ge之间 浓度等）。 应变鳍片可以位于pFET区域中，并且松弛鳍片可以位于半导体器件的nFET区域中。 因此，可以通过pFET区域中的应变鳍实现移动性益处，而移动性负载可以由nFET区域中的松散鳍限制。 应变翅片的高度相对于在外延形成的Si覆盖层中或在外延形成的Ge覆盖层中发生生长缺陷的临界厚度更大。

    U-shaped semiconductor structure
    7.
    发明授权
    U-shaped semiconductor structure 有权
    U形半导体结构

    公开(公告)号：US09318580B2

    公开(公告)日：2016-04-19

    申请号：US14590327

    申请日：2015-01-06

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Pouya Hashemi ,  Ali Khakifirooz

    IPC: H01L29/66 ,  H01L21/02 ,  H01L29/78

    CPC classification number: H01L29/66795 ,  H01L21/02494 ,  H01L21/02587 ,  H01L29/7853

    Abstract: A method for forming a U-shaped semiconductor device includes growing a U-shaped semiconductor material along sidewalls and bottoms of trenches, which are formed in a crystalline layer. The U-shaped semiconductor material is anchored, and the crystalline layer is removed. Backfilling is formed underneath the U-shaped semiconductor material with a dielectric material for support. A semiconductor device is formed with the U-shaped semiconductor material.

    Abstract translation: 形成U型半导体器件的方法包括沿形成在晶体层中的沟槽的侧壁和底部生长U形半导体材料。 U型半导体材料被锚固，并且去除晶体层。 在具有用于支撑的电介质材料的U形半导体材料下形成回填。 半导体器件由U形半导体材料形成。

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