公开(公告)号：US20170317161A1

公开(公告)日：2017-11-02

申请号：US15142332

申请日：2016-04-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ran Yan ,  Ming-Cheng Chang ,  Ralf Richter

IPC: H01L49/02

CPC classification number: H01L28/84 ,  H01L21/76283 ,  H01L28/40 ,  H01L28/82

Abstract: The present disclosure provides a method of forming a capacitor structure and a capacitor structure. A semiconductor-on-insulator substrate is provided comprising a semiconductor layer, a buried insulating material layer and a semiconductor substrate material. A shallow trench isolation structure defining a first active region on the SOI substrate is formed, the first active region having a plurality of trenches formed therein. Within each trench, the semiconductor substrate material is exposed on inner sidewalls and a bottom face. A layer of insulating material covering the exposed semiconductor substrate material is formed, and an electrode material is deposited on the layer of insulating material in the first active region.

公开(公告)号：US20170250181A1

公开(公告)日：2017-08-31

申请号：US15054355

申请日：2016-02-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ming-Cheng Chang ,  Ran Yan ,  Bo Bai

IPC: H01L27/088 ,  H01L21/3213 ,  H01L21/306 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/30604 ,  H01L21/32133 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475

Abstract: A semiconductor device including a semiconductor layer, a plurality of semiconductor fins formed on a surface of the semiconductor layer and a plurality of gate electrodes formed over the surface of the semiconductor layer is provided. The semiconductor fins extend in parallel to each other along a first direction parallel to the surface of the semiconductor layer and have a first height in a second direction that is perpendicular to the first direction, and the gate electrodes comprise longitudinal portions extending parallel to the semiconductor fins along the first direction and, in particular, having a second height in the second direction lower than the first height.

公开(公告)号：US09614003B1

公开(公告)日：2017-04-04

申请号：US14918736

申请日：2015-10-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Yu-Teh Chiang ,  Ran Yan

IPC: H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01L27/22

CPC classification number: H01L27/228 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: The present disclosure provides a memory device structure including a wafer substrate, a magnetic tunnel junction (MTJ) formed by a first magnetic layer, a second magnetic layer, and a thin non-magnetic layer stacked along a first direction perpendicular to an upper surface of the wafer substrate above which the MTJ is formed, the non-magnetic layer being interposed between the first magnetic layer and the second magnetic layer, a first contact electrically coupled to the first magnetic layer, and a second contact electrically coupled to the second magnetic layer.

公开(公告)号：US20170069550A1

公开(公告)日：2017-03-09

申请号：US14844163

申请日：2015-09-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ran Yan ,  Alban Zaka ,  Pei-Yu Chou

IPC: H01L21/84 ,  H01L21/8238 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/762 ,  H01L21/311

CPC classification number: H01L21/823878 ,  H01L21/02164 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/31055 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/092

Abstract: In a first aspect, the present disclosure provides a method of forming a semiconductor device, including providing an SOI structure comprising a base substrate, a buried insulating material layer formed on the base substrate and an active semiconductor layer formed on the buried insulating structure, forming a germanium-comprising layer on an exposed surface of the active semiconductor layer, forming a trench isolation structure, the trench isolation structure extending through the germanium-comprising layer and the active semiconductor layer, performing an annealing process after the trench isolation structure is formed, the annealing process resulting in an oxide layer disposed on a germanium-comprising active layer which is formed on the buried insulating material layer, and removing the oxide layer for exposing an upper surface of the germanium-comprising active layer.

Abstract translation: 在第一方面，本公开内容提供了一种形成半导体器件的方法，包括提供SOI结构，其包括基底基板，形成在基底基板上的掩埋绝缘材料层和形成在掩埋绝缘结构上的有源半导体层，形成 在有源半导体层的暴露表面上的含锗层，形成沟槽隔离结构，所述沟槽隔离结构延伸穿过含锗层和有源半导体层，在形成沟槽隔离结构之后进行退火处理， 所述退火工艺导致设置在形成在所述掩埋绝缘材料层上的含锗活性层上的氧化物层，以及去除所述氧化物层以暴露所述含锗活性层的上表面。

公开(公告)号：US09029214B2

公开(公告)日：2015-05-12

申请号：US13740974

申请日：2013-01-14

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Jan Hoentschel ,  Stefan Flachowsky ,  Nicolas Sassiat ,  Ran Yan

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/665 ,  H01L21/823443 ,  H01L21/823468 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/78

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided herein. In an embodiment, a method for fabricating an integrated circuit includes forming over a semiconductor substrate a gate structure. The method further includes depositing a non-conformal spacer material around the gate structure. A protection mask is formed over the non-conformal spacer material. The method etches the non-conformal spacer material and protection mask to form a salicidation spacer. Further, a self-aligned silicide contact is formed adjacent the salicidation spacer.

Abstract translation: 本文提供用于制造集成电路的集成电路和方法。 在一个实施例中，制造集成电路的方法包括在半导体衬底上形成栅极结构。 该方法还包括在栅极结构周围沉积非共形间隔物材料。 在非保形间隔物材料上形成保护罩。 该方法蚀刻非共形间隔物材料和保护掩模以形成防腐隔离物。 此外，邻近该盐化隔离层形成自对准的硅化物接触。

公开(公告)号：US20150021703A1

公开(公告)日：2015-01-22

申请号：US13943229

申请日：2013-07-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ran Yan ,  Nicolas Sassiat ,  Jan Hoentschel ,  Torben Balzer

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/16 ,  H01L29/66

CPC classification number: H01L27/092 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28238 ,  H01L21/823412 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/513 ,  H01L29/66477 ,  H01L29/66651 ,  H01L29/78

Abstract: In various aspects, methods of forming a semiconductor device and semiconductor devices are provided. In some illustrative embodiments herein, a silicon/germanium layer is provided on a semiconductor substrate. On the silicon/germanium layer, at least one insulating material layer is formed. After having performed a thermal annealing process, the at least one insulating material layer is removed in subsequent process sequences such that the silicon/germanium layer is at least partially exposed. In further processing sequences which are to be subsequently applied, a gate electrode is formed on the exposed silicon/germanium layer.

Abstract translation: 在各个方面，提供了形成半导体器件和半导体器件的方法。 在本文的一些说明性实施例中，硅/锗层设置在半导体衬底上。 在硅/锗层上形成至少一个绝缘材料层。 在进行热退火处理之后，在随后的处理顺序中除去至少一个绝缘材料层，使得硅/锗层至少部分暴露。 在随后施加的另外的处理顺序中，在暴露的硅/锗层上形成栅电极。

公开(公告)号：US20140197498A1

公开(公告)日：2014-07-17

申请号：US13740974

申请日：2013-01-14

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Jan Hoentschel ,  Stefan Flachowsky ,  Nicolas Sasiat ,  Ran Yan

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/665 ,  H01L21/823443 ,  H01L21/823468 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/78

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided herein. In an embodiment, a method for fabricating an integrated circuit includes forming over a semiconductor substrate a gate structure. The method further includes depositing a non-conformal spacer material around the gate structure. A protection mask is formed over the non-conformal spacer material. The method etches the non-conformal spacer material and protection mask to form a salicidation spacer. Further, a self-aligned silicide contact is formed adjacent the salicidation spacer.

Abstract translation: 本文提供用于制造集成电路的集成电路和方法。 在一个实施例中，制造集成电路的方法包括在半导体衬底上形成栅极结构。 该方法还包括在栅极结构周围沉积非共形间隔物材料。 在非保形间隔物材料上形成保护罩。 该方法蚀刻非共形间隔物材料和保护掩模以形成防腐隔离物。 此外，邻近该盐化隔离层形成自对准的硅化物接触。

公开(公告)号：US09748236B1

公开(公告)日：2017-08-29

申请号：US15054355

申请日：2016-02-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ming-Cheng Chang ,  Ran Yan ,  Bo Bai

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/3213 ,  H01L21/306

CPC classification number: H01L27/0886 ,  H01L21/30604 ,  H01L21/32133 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475

Abstract: A semiconductor device including a semiconductor layer, a plurality of semiconductor fins formed on a surface of the semiconductor layer and a plurality of gate electrodes formed over the surface of the semiconductor layer is provided. The semiconductor fins extend in parallel to each other along a first direction parallel to the surface of the semiconductor layer and have a first height in a second direction that is perpendicular to the first direction, and the gate electrodes comprise longitudinal portions extending parallel to the semiconductor fins along the first direction and, in particular, having a second height in the second direction lower than the first height.

公开(公告)号：US20170148850A1

公开(公告)日：2017-05-25

申请号：US15428509

申请日：2017-02-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Yu-Teh Chiang ,  Ran Yan

IPC: H01L27/22 ,  G11C11/16 ,  H01L43/10 ,  H01L43/02 ,  H01L43/08

Abstract: A memory device structure includes a wafer substrate and a magnetic tunnel junction (MTJ) positioned above an upper surface of the wafer substrate. The MTJ includes a first magnetic layer, a second magnetic layer laterally adjacent the first magnetic layer, and a nonmagnetic layer interposed between the first and second magnetic layers, wherein the first magnetic layer, the nonmagnetic layer and the second magnetic layer comprise a substantially vertical layer stack that extends along a first direction that is substantially perpendicular to the upper surface of the wafer substrate. A first contact is electrically coupled to the first magnetic layer and a second contact is electrically coupled to the second magnetic layer.

公开(公告)号：US09461145B2

公开(公告)日：2016-10-04

申请号：US14503810

申请日：2014-10-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ran Yan ,  Jan Hoentschel ,  Martin Gerhardt

IPC: H01L21/3213 ,  G03F1/36 ,  H01L29/66 ,  H01L21/762 ,  H01L29/165 ,  H01L29/08 ,  H01L21/02 ,  H01L29/06 ,  H01L29/78 ,  H01L29/49 ,  G03F1/72 ,  H01L21/033

CPC classification number: H01L29/66545 ,  G03F1/72 ,  H01L21/02164 ,  H01L21/0337 ,  H01L21/32139 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/4916 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848

Abstract: Enlarging the dummy electrode to the STI top width size by OPC cut mask correction and the resulting device are disclosed. Embodiments include forming an STI region in a silicon substrate, the STI region having a top width; and forming a dummy electrode on the STI region and a gate electrode on the silicon substrate, the dummy electrode having a width greater than or equal to the STI region top width.

Abstract translation: 通过OPC切割掩模校正将虚拟电极放大到STI顶部宽度尺寸，并且公开了所得到的器件。 实施例包括在硅衬底中形成STI区域，STI区域具有顶部宽度; 在STI区域上形成虚设电极，在硅衬底上形成栅电极，该虚拟电极的宽度大于或等于STI区域顶部宽度。