公开(公告)号：US20140054547A1

公开(公告)日：2014-02-27

申请号：US13914514

申请日：2013-06-10

Applicant: GLOBALFOUNDRIES Inc. ,  IMEC

Inventor： Geert Eneman ,  David Brunco ,  Geert Hellings

IPC: H01L29/78

CPC classification number: H01L29/785 ,  B82Y10/00 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/775 ,  H01L29/7781

Abstract: The disclosed technology relates to transistors having a strained quantum well for carrier confinement, and a method for manufacturing thereof. In one aspect, a FinFET or a planar FET device comprises a semiconductor substrate, a strain-relaxed buffer layer comprising Ge formed on the semiconductor substrate, a channel layer formed on the strain-relaxed buffer layer, and a strained quantum barrier layer comprising SiGe interposed between and in contact with the strain-relaxed buffer layer and the channel layer. The compositions of the strain-relaxed buffer layer, the strained quantum barrier layer and the channel layer are chosen such that a band offset of the channel layer and a band offset of the strained quantum barrier layer have opposite signs with respect to the strain-relaxed buffer layer.

Abstract translation: 所公开的技术涉及具有用于载流子限制的应变量子阱的晶体管及其制造方法。 在一个方面，FinFET或平面FET器件包括半导体衬底，形成在半导体衬底上的Ge的应变松弛缓冲层，形成在应变弛缓缓冲层上的沟道层和包含SiGe的应变量子势垒层 介于与应变松弛缓冲层和沟道层接触之间。 应变松弛缓冲层，应变量子势垒层和沟道层的组成被选择为使得沟道层的带偏移和应变量子势垒层的带偏移相对于应变松弛具有相反的符号 缓冲层。

公开(公告)号：US09698262B2

公开(公告)日：2017-07-04

申请号：US15072130

申请日：2016-03-16

Applicant: IMEC VZW ,  GLOBALFOUNDRIES INC.

Inventor： Bartlomiej Pawlak ,  Geert Eneman

IPC: H01L29/74 ,  H01L29/80 ,  H01L29/94 ,  H01L21/00 ,  H01L21/338 ,  H01L21/337 ,  H01L29/78 ,  H01L21/765 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L29/7827 ,  H01L21/76 ,  H01L21/765 ,  H01L29/0607 ,  H01L29/0657 ,  H01L29/1083 ,  H01L29/42356

Abstract: A vertical FinFET semiconductor device and a method of forming the same are disclosed. In one aspect, the semiconductor device includes a current-blocking structure formed over a semiconductor structure and a semiconductor fin formed on the current-blocking structure. The current blocking structure includes a first layer of a first conductive type, a layer of a second conductive type over the first layer, and a second layer of the first conductive type over the layer of the second conductive type. The semiconductor fin has a doped bottom portion contacting the current-blocking structure, a doped top portion formed vertically opposite to the doped bottom portion and a channel portion vertically interposed between the doped bottom portion and the doped top portion.

公开(公告)号：US09064702B2

公开(公告)日：2015-06-23

申请号：US13956273

申请日：2013-07-31

Applicant: IMEC ,  GLOBALFOUNDRIES INC.

Inventor： David Brunco ,  Geert Eneman

IPC: H01L21/31 ,  H01L21/469 ,  H01L21/02 ,  H01L29/78 ,  H01L21/324

CPC classification number: H01L21/02565 ,  H01L21/0243 ,  H01L21/02521 ,  H01L21/02664 ,  H01L21/324 ,  H01L29/7843

Abstract: A method for reducing defects in an active device area of a semiconductor device during fabrication is disclosed. In one aspect, the method comprises providing the active device area adjacent an isolation structure, wherein a substantially planar surface is formed over the isolation structure and the active device area, forming a patterned stress-inducing layer over the substantially planar surface, forming at least one screening layer between the patterned stress-inducing layer and the substantially planar surface, where the screening layer is configured to screen part of the stress field induced by the patterned stress-inducing layer, performing an anneal process after forming the patterned stress-inducing layer on the substantially planar surface, so as to induce a movement of the defects towards a contact interface between the active device area and the isolation structure, and removing the patterned stress-inducing layer from the substantially planar surface.

Abstract translation: 公开了一种用于在制造期间减少半导体器件的有源器件区域中的缺陷的方法。 在一个方面，该方法包括提供邻近隔离结构的有源器件区域，其中基本平坦的表面形成在隔离结构和有源器件区域之上，在基本平坦的表面上形成图案化的应力诱导层，至少形成 在图案化的应力诱导层和基本上平坦的表面之间的一个屏蔽层，其中屏蔽层被配置为屏蔽由图案化的应力诱导层感应的应力场的一部分，在形成图案化的应力诱导层之后执行退火工艺 在基本上平坦的表面上，以引起缺陷朝向有源器件区域和隔离结构之间的接触界面的移动，以及从基本平坦的表面移除图案化的应力诱导层。

公开(公告)号：US09006705B2

公开(公告)日：2015-04-14

申请号：US13914514

申请日：2013-06-10

Applicant: IMEC ,  GLOBALFOUNDRIES Inc.

Inventor： Geert Eneman ,  David Brunco ,  Geert Hellings

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/775 ,  H01L29/778 ,  H01L29/161 ,  H01L29/165 ,  H01L29/10 ,  B82Y10/00

CPC classification number: H01L29/785 ,  B82Y10/00 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/775 ,  H01L29/7781

Abstract: The disclosed technology relates to transistors having a strained quantum well for carrier confinement, and a method for manufacturing thereof. In one aspect, a FinFET or a planar FET device comprises a semiconductor substrate, a strain-relaxed buffer layer comprising Ge formed on the semiconductor substrate, a channel layer formed on the strain-relaxed buffer layer, and a strained quantum barrier layer comprising SiGe interposed between and in contact with the strain-relaxed buffer layer and the channel layer. The compositions of the strain-relaxed buffer layer, the strained quantum barrier layer and the channel layer are chosen such that a band offset of the channel layer and a band offset of the strained quantum barrier layer have opposite signs with respect to the strain-relaxed buffer layer.

Abstract translation: 所公开的技术涉及具有用于载流子限制的应变量子阱的晶体管及其制造方法。 在一个方面，FinFET或平面FET器件包括半导体衬底，形成在半导体衬底上的Ge的应变松弛缓冲层，形成在应变弛缓缓冲层上的沟道层和包含SiGe的应变量子势垒层 介于与应变松弛缓冲层和沟道层接触之间。 应变松弛缓冲层，应变量子势垒层和沟道层的组成被选择为使得沟道层的带偏移和应变量子势垒层的带偏移相对于应变松弛具有相反的符号 缓冲层。

公开(公告)号：US20140038426A1

公开(公告)日：2014-02-06

申请号：US13956273

申请日：2013-07-31

Applicant: Globalfoundries Inc. ,  IMEC

Inventor： David Brunco ,  Geert Eneman

IPC: H01L21/02

CPC classification number: H01L21/02565 ,  H01L21/0243 ,  H01L21/02521 ,  H01L21/02664 ,  H01L21/324 ,  H01L29/7843

Abstract: A method for reducing defects in an active device area of a semiconductor device during fabrication is disclosed. In one aspect, the method comprises providing the active device area adjacent an isolation structure, wherein a substantially planar surface is formed over the isolation structure and the active device area, forming a patterned stress-inducing layer over the substantially planar surface, forming at least one screening layer between the patterned stress-inducing layer and the substantially planar surface, where the screening layer is configured to screen part of the stress field induced by the patterned stress-inducing layer, performing an anneal process after forming the patterned stress-inducing layer on the substantially planar surface, so as to induce a movement of the defects towards a contact interface between the active device area and the isolation structure, and removing the patterned stress-inducing layer from the substantially planar surface.

Abstract translation: 公开了一种用于在制造期间减少半导体器件的有源器件区域中的缺陷的方法。 在一个方面，该方法包括提供邻近隔离结构的有源器件区域，其中基本平坦的表面形成在隔离结构和有源器件区域之上，在基本平坦的表面上形成图案化的应力诱导层，至少形成 在图案化的应力诱导层和基本上平坦的表面之间的一个屏蔽层，其中屏蔽层被配置为屏蔽由图案化的应力诱导层感应的应力场的一部分，在形成图案化的应力诱导层之后执行退火工艺 在基本上平坦的表面上，以引起缺陷朝向有源器件区域和隔离结构之间的接触界面的移动，以及从基本平坦的表面移除图案化的应力诱导层。

公开(公告)号：US11088263B2

公开(公告)日：2021-08-10

申请号：US16893233

申请日：2020-06-04

Applicant: IMEC vzw

Inventor： Anabela Veloso ,  Geert Eneman

IPC: H01L29/66 ,  H01L29/16 ,  H01L29/417

Abstract: The disclosed technology relates generally to semiconductor processing and more particularly to a method of forming a vertical field-effect transistor device. According to an aspect, a method of forming a vertical field-effect transistor device comprises forming on a substrate a vertical semiconductor structure protruding above the substrate and comprising a lower source/drain portion, an upper source/drain portion and a channel portion arranged between the lower source/drain portion and the upper source/drain portion. The method additionally comprises forming on the channel portion an epitaxial semiconductor stressor layer enclosing the channel portion, wherein the stressor layer and the channel portion are lattice mismatched, forming an insulating layer and a sacrificial structure, wherein the sacrificial structure encloses the channel portion with the stressor layer formed thereon and wherein the insulating layer embeds the semiconductor structure and the sacrificial structure, forming in the insulating layer an opening exposing a surface portion of the sacrificial structure, and etching the sacrificial structure through the opening in the insulating layer, thereby forming a cavity exposing the stressor layer enclosing the channel portion. The method further comprises, subsequent to etching the sacrificial structure, etching the stressor layer in the cavity, and subsequent to etching the stressor layer, forming a gate stack in the cavity, wherein the gate stack encloses the channel portion of the vertical semiconductor structure.

公开(公告)号：US09171904B2

公开(公告)日：2015-10-27

申请号：US14086486

申请日：2013-11-21

Applicant: IMEC

Inventor： Geert Eneman ,  Benjamin Vincent ,  Voon Yew Thean

IPC: H01L21/77 ,  H01L29/10 ,  H01L21/8238

CPC classification number: H01L27/0886 ,  H01L21/823821 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7842 ,  H01L29/7849

Abstract: A FinFET device and a method for manufacturing a FinFET device is provided. An example device may comprise a substrate including at least two fin structures. Each of the at least two fin structures may be in contact with a source and drain region and each of the at least two fin structures may include a strain relaxed buffer (SRB) overlying and in contact with the substrate and an upper layer overlying and in contact with the SRB. The composition of the upper layer and the SRB may be selected such that the upper layer of a first fin structure is subjected to a first mobility enhancing strain in the as-grown state, the first mobility enhancing strain being applied in a longitudinal direction from the source region to the drain region and where at least an upper part of the upper layer of a second fin structure is strain-relaxed.

Abstract translation: 提供FinFET器件和制造FinFET器件的方法。 示例性装置可以包括包括至少两个翅片结构的基板。 所述至少两个翅片结构中的每一个可以与源极和漏极区域接触，并且所述至少两个鳍结构中的每一个可以包括覆盖并与衬底接触的应变松弛缓冲器（SRB），并且上层覆盖和 与SRB联系。 可以选择上层和SRB的组成，使得第一鳍结构的上层在生长状态下经受第一迁移率增强应变，第一迁移率增强应变沿纵向施加于 源极区到漏极区，并且其中第二鳍结构的上层的至少上部被应变松弛。

公开(公告)号：US20240178051A1

公开(公告)日：2024-05-30

申请号：US18524355

申请日：2023-11-30

Applicant: IMEC VZW

Inventor： Anabela Veloso ,  Rongmei Chen ,  An De Keersgieter ,  Geert Eneman ,  Philippe Matagne

IPC: H01L21/74 ,  H01L21/768

CPC classification number: H01L21/743 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76879 ,  H01L21/823431

Abstract: A method includes: forming a structure on a frontside of a substrate, the structure including a first and a second source/drain body located in a first and a second source/drain region, respectively, and a channel body including a channel layer extending between the first and second source/drain bodies; forming a trench beside the first source/drain region by etching the substrate such that a lower portion of the trench undercuts the first source/drain region; forming a liner on the trench; forming an opening in the liner underneath the first source/drain region; and forming a dummy interconnect in the trench; where the method further includes exposing the dummy interconnect from a backside of the substrate; removing the dummy interconnect selectively to the liner; and forming a buried interconnect of a conductive material in the trench, where the buried interconnect is connected to the first source/drain body via the opening in the liner.

公开(公告)号：US20210336057A1

公开(公告)日：2021-10-28

申请号：US17241318

申请日：2021-04-27

Applicant: IMEC VZW

Inventor： Geert Eneman ,  Basoene Briggs ,  An De Keersgieter ,  Anabela Veloso ,  Paola Favia

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/165 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: A semiconductor structure comprises a semiconductor substrate having a top layer and one or more semiconductor monocrystalline nanostructures. Each nanostructure has a first and a second extremity defining an axis parallel to the top surface of the semiconductor substrate and separated therefrom by a distance, and a source structure epitaxially grown on the first extremity and a drain structure epitaxially grown on the second extremity. The source and drain structures are made of a p-doped (or alternatively n-doped) semiconductor monocrystalline material having a smaller (or alternatively larger) unstrained lattice constant than the unstrained lattice constant of the semiconductor monocrystalline material making the semiconductor monocrystalline nanostructure on which they are grown, thereby creating compressive (or alternatively tensile) strain in that semiconductor monocrystalline nanostructure.

公开(公告)号：US20170033183A1

公开(公告)日：2017-02-02

申请号：US15218922

申请日：2016-07-25

Applicant: IMEC VZW

Inventor： Bernardette Kunert ,  Robert Langer ,  Geert Eneman

IPC: H01L29/10 ,  H01L29/04 ,  H01L29/161 ,  H01L21/306 ,  H01L21/02 ,  H01L29/423 ,  H01L21/324

CPC classification number: H01L29/1054 ,  H01L21/02381 ,  H01L21/02455 ,  H01L21/02469 ,  H01L21/02513 ,  H01L21/02524 ,  H01L21/02532 ,  H01L21/30612 ,  H01L21/3245 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/161 ,  H01L29/42356 ,  H01L29/775

Abstract: Disclosed herein is a semiconductor structure including: (i) a monocrystalline substrate having a top surface, (ii) a non-crystalline structure overlying the monocrystalline substrate and including an opening having a width smaller than 10 microns and exposing part of the top surface of the monocrystalline substrate. The semiconductor structure also includes (iii) a buffer structure having a bottom surface abutting the part and a top surface having less than 108 threading dislocations per cm2, the buffer structure being made of a material having a first lattice constant. The semiconductor structure also includes (iv) one or more group IV monocrystalline structures abutting the buffer structure and that are made of a material having a second lattice constant, different from the first lattice constant.

Abstract translation: 本文公开了一种半导体结构，其包括：（i）具有顶表面的单晶衬底，（ii）覆盖在单晶衬底上的非晶体结构，并且包括具有小于10微米的宽度的开口，并暴露部分顶部表面的 单晶衬底。 半导体结构还包括（iii）具有邻接部分的底表面的缓冲结构和每平方厘米具有小于108个穿透位错的顶表面，该缓冲结构由具有第一晶格常数的材料制成。 半导体结构还包括（iv）邻接缓冲结构的一个或多个IV族单晶结构，并且由具有与第一晶格常数不同的第二晶格常数的材料制成。