公开(公告)号：US20230386928A1

公开(公告)日：2023-11-30

申请号：US18322213

申请日：2023-05-23

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Naoto Horiguchi ,  Julien Ryckaert

IPC: H01L21/8234 ,  H01L29/66

CPC classification number: H01L21/823456 ,  H01L21/823412 ,  H01L21/823431 ,  H01L29/66439

Abstract: The present disclosure relates to a method for forming a stacked transistor device comprising a lower NSHFET structure and an upper FinFET structure including: forming a fin structure comprising: a lower device sub-stack comprising a number of lower channel nanosheets, a middle insulating layer, an upper device sub-stack comprising an upper channel layer, and a capping layer; forming a process layer embedding the fin structure; subsequent to forming the process layer, removing the capping layer from the fin structure to define a gap exposing the upper device sub-stack; forming spacer layers on opposite side surfaces of the gap to form a reduced-width gap; splitting the upper channel layer by etching back an upper surface thereof via the reduced-width gap to form two upper channel fins; subsequent to forming the upper channel fins, removing the spacer layers; and thereafter: forming a gate structure; and forming source and drain regions for the lower channel nanosheets and the upper channel fins.

公开(公告)号：US20230197522A1

公开(公告)日：2023-06-22

申请号：US18065130

申请日：2022-12-13

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Anne Vandooren ,  Julien Ryckaert ,  Naoto Horiguchi

IPC: H01L21/8234 ,  H01L29/66

CPC classification number: H01L21/823437 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/42392

Abstract: The disclosure relates to a method for forming a semiconductor device. The method includes forming a device layer stack on a substrate, the device layer stack having a first sub-stack comprising a first sacrificial layer and on the first sacrificial layer a channel layer defining a topmost layer of the first sub-stack, and a second sub-stack on the first sub-stack and including a first sacrificial layer defining a bottom layer of the second sub-stack, and a second sacrificial layer on the first sacrificial layer, wherein said first sacrificial layers are formed of a first sacrificial semiconductor material, the second sacrificial layer is formed of a second sacrificial semiconductor material, and the channel layer is formed of a semiconductor channel material, and wherein a thickness of the second sub-stack exceeds a thickness of the first sacrificial layer of the first sub-stack. The method comprises replacing the second sacrificial layer of the second sub-stack with a dielectric layer; forming recesses in the device layer stack by laterally etching back end surfaces of the first sacrificial layers of the first and second sub-stacks from opposite sides of the sacrificial gate structure; and forming inner spacers in the recesses.

公开(公告)号：US20230197514A1

公开(公告)日：2023-06-22

申请号：US18066400

申请日：2022-12-15

Applicant: IMEC VZW

Inventor： Victor Hugo Vega Gonzalez ,  Bilal Chehab ,  Julien Ryckaert ,  Zsolt Tokei ,  Serge Biesemans ,  Naoto Horiguchi

IPC: H01L21/768 ,  H01L21/3213 ,  H01L23/522

CPC classification number: H01L21/76897 ,  H01L21/32139 ,  H01L21/76885 ,  H01L23/5226 ,  H01L21/32136 ,  H01L27/092

Abstract: The disclosure relates to a metallization process for an integrated circuit. One example metallization process includes a method for forming an integrated circuit that includes providing a semiconductor structure having two transistor structures, a gate structure, electrically conductive contacts, a first electrically conductive line, a first electrically conductive via, a second electrically conductive via. The method further includes providing a planar dielectric material in contact with the first electrically conductive line, forming an opening in the planar dielectric material, filling the opening with a planar electrically conductive material, forming an electrically conductive layer arranged within a second metallization level, the electrically conductive layer being in physical contact with the planar dielectric material and in physical and electrical contact with the electrically conductive material, providing a hard mask comprising a set of parallel lines, and etching the electrically conductive layer and the planar electrically conductive material by using the hard mask lines as a mask.

公开(公告)号：US11462443B2

公开(公告)日：2022-10-04

申请号：US17110604

申请日：2020-12-03

Applicant: IMEC vzw

Inventor： Eugenio Dentoni Litta ,  Juergen Boemmels ,  Julien Ryckaert ,  Naoto Horiguchi ,  Pieter Weckx

IPC: H01L21/8238 ,  H01L27/092 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L21/02 ,  H01L21/762 ,  H01L29/66

Abstract: In one aspect, a method of forming a semiconductor device, can comprise forming a first transistor structure and a second transistor structure separated by a trench. The first and the second transistor structures can comprise a plurality of stacked nanosheets forming a channel structure, and a source portion and a drain portion horizontally separated by the channel structure. A first and a second spacer can beformed in the trench at sidewalls of the transistor structures, both protruding above a top surface of the transistor structures. The method can comprise applying a first mask layer including an opening exposing the first spacer at a first source/drain portion of the first transistor structure and covering the second spacer, partially etching the exposed first spacer through the opening, exposing at least parts of a sidewall of the first source/drain portion of the first transistor structure, and removing the mask layer. The method can further comprise depositing a contact material over the transistor structures and the first and second spacer, filling the trench and contacting the first source/drain portion of the first transistor structure, and etching back the contact material layer below a top surface of the second spacer.

公开(公告)号：US20180330997A1

公开(公告)日：2018-11-15

申请号：US15977381

申请日：2018-05-11

Applicant: IMEC VZW ,  Vrije Universiteit Brussel

Inventor： Julien Ryckaert ,  Naoto Horiguchi ,  Dan Mocuta ,  Trong Huynh Bao

IPC: H01L21/8238 ,  H01L21/285 ,  H01L21/306 ,  H01L21/308 ,  H01L21/762 ,  H01L23/528 ,  H01L27/11 ,  H01L27/092 ,  H01L29/06 ,  H01L29/45 ,  H01L29/78

Abstract: The disclosed technology generally relates to semiconductor fabrication and more particularly to forming vertical transistor devices. In an aspect, a method of forming a vertical transistor device includes forming, on a substrate, a fin comprising a stack including a first layer, a second layer formed above the first layer and a third layer formed above the second layer. The method additionally includes forming a gate layer serving as an etch mask above the third layer. The method further includes etching the second and third layers of the fin using the gate layer as the etch mask to form a pillar. First and third layers of the pillar define a source region and a drain region, respectively, of the vertical transistor device. A second layer of the pillar defines a channel region of the vertical transistor device. The gate layer comprises a gate electrode arranged on at least one sidewall of the second layer.

公开(公告)号：US20150111351A1

公开(公告)日：2015-04-23

申请号：US14521083

申请日：2014-10-22

Applicant: IMEC VZW

Inventor： Min-Soo Kim ,  Guillaume Boccardi ,  Soon Aik Chew ,  Naoto Horiguchi

IPC: H01L21/8238 ,  H01L21/762 ,  H01L21/02 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L21/823821 ,  H01L21/02126 ,  H01L21/76205 ,  H01L21/82385 ,  H01L21/823878 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7851

Abstract: A method for manufacturing a field effect transistor of a non-planar type, comprising providing a substrate having an initially planar front main surface, and providing shallow trench isolation structures in the substrate on the front surface, thereby defining a plurality of fin structures in the substrate between the shallow trench isolation structures. Top surfaces of the shallow trench isolation structures and the fin structures abut on a common planar surface, and sidewalls of the fin structures are fully concealed by the shallow trench isolation structures. The method also includes forming a dummy gate structure over a central portion of the plurality of fin structures on the common planar surface, forming dielectric spacer structures around the dummy gate structure, and removing the dummy gate structure, thereby leaving a gate trench defined by the dielectric spacer structures. Further, the method includes removing an upper portion of at least two shallow trench isolation structures to expose at least a portion of the sidewalls of the fin structures within the gate trench, and forming a final gate stack in the gate trench.

Abstract translation: 一种用于制造非平面型场效应晶体管的方法，包括提供具有初始平面的前主表面的基板，并且在所述前表面上的所述基板中提供浅沟槽隔离结构，从而在所述基板中限定多个鳍结构 衬底之间的浅沟槽隔离结构。 浅沟槽隔离结构和翅片结构的顶表面邻接在共同的平坦表面上，翅片结构的侧壁被浅沟槽隔离结构完全隐藏。 该方法还包括在公共平面上的多个翅片结构的中心部分上形成虚拟栅极结构，在虚拟栅极结构周围形成介质间隔物结构，以及去除伪栅极结构，由此留下由 电介质间隔结构。 此外，该方法包括去除至少两个浅沟槽隔离结构的上部以暴露栅极沟槽内的翅片结构的侧壁的至少一部分，以及在栅极沟槽中形成最终的栅极叠层。

公开(公告)号：US20240136225A1

公开(公告)日：2024-04-25

申请号：US18486370

申请日：2023-10-12

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Hans Mertens ,  Zsolt Tokei ,  Naoto Horiguchi

IPC: H01L21/768 ,  H01L23/528 ,  H01L29/40

CPC classification number: H01L21/76879 ,  H01L21/76802 ,  H01L23/5286 ,  H01L29/401

Abstract: A method provided for interconnecting a buried wiring line and a source/drain body. The method includes: forming a fin structure on a substrate, the fin structure comprising at least one channel layer; forming a buried wiring line in a trench extending alongside the fin structure, wherein the buried wiring line is capped by a first insulating layer structure; forming a source/drain body on the at least one channel layer by epitaxy; forming a via hole in the first insulating layer structure to expose an upper surface of the buried wiring line; forming a metal via in the via hole; forming a second insulating layer structure over the first insulating layer structure, wherein a contact opening is defined in the second insulating layer structure to expose the source/drain body and an upper via portion of the metal via; and forming a source/drain contact in the contact opening, on the upper via portion and the source/drain body, thereby inter-connecting the buried wiring line and the source/drain body.

公开(公告)号：US20230197830A1

公开(公告)日：2023-06-22

申请号：US18065353

申请日：2022-12-13

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Anne Vandooren ,  Naoto Horiguchi

IPC: H01L29/66 ,  H01L21/3213 ,  H01L21/311 ,  H01L29/40 ,  H01L21/8238

CPC classification number: H01L29/66545 ,  H01L21/3213 ,  H01L21/31144 ,  H01L29/6656 ,  H01L29/66553 ,  H01L29/6653 ,  H01L29/66439 ,  H01L29/401 ,  H01L21/823807 ,  H01L21/823871 ,  H01L29/42392

Abstract: A method for forming a stacked field-effect transistor device is provided. The method including: forming a bottom FET device comprising a bottom gate electrode arranged; forming a bonding layer of dielectric bonding material over the bottom FET device; and forming a top FET device on the bonding layer, including: forming a fin structure comprising a channel layer; etching through the bonding layer to form a bonding layer pattern comprising the dielectric bonding material underneath the fin structure; forming a dummy gate and a dummy gate spacer layer; forming cuts in the fin structure and the bonding layer pattern; forming recesses underneath a fin structure portion preserved underneath the dummy gate by laterally etching back side surface portions of a bonding layer pattern portion; removing the first spacer layer and subsequently forming a second spacer layer covering the side surfaces of the dummy gate and filling the recesses; removing the dummy gate selectively to the second spacer layer to form an upper gate cavity portion exposing the fin structure portion; forming a lower gate cavity portion exposing an upper surface of the bottom gate electrode, comprising removing the bonding layer pattern portion by subjecting the bonding layer pattern portion to an isotropic etching process via the upper gate cavity; and forming a gate electrode in the upper and lower gate cavity portions.

公开(公告)号：US20230178640A1

公开(公告)日：2023-06-08

申请号：US18060954

申请日：2022-12-01

Applicant: IMEC VZW

Inventor： Aryan Afzalian ,  Julien Ryckaert ,  Naoto Horiguchi

IPC: H01L29/775 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/775 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439

Abstract: A FET device (100) is provided, the FET device including a substrate (102), a source body (120), a drain body (130) and a set of vertically spaced apart channel layers (150) extending between the source and drain body in a first direction along the substrate (102), the source body (120) comprising a common source body portion (122) arranged at a first lateral side of the set of channel layers (150) and a set of vertically spaced apart source prongs (124) protruding from the common source body portion (122) in a second direction along the substrate (102), transverse to the first direction, the drain body (130) comprising a common source body portion (132) arranged at the first lateral side of the set of channel layers (150) and a set of drain prongs (134) protruding from the common drain body portion (132) in the second direction; and a gate body (140) comprising a common gate body portion (142) arranged at a second lateral side of the channel layer (150), opposite the first lateral side, and a set of gate prongs (144) protruding from the common gate body gate portion (142) in a third direction along the substrate (102), opposite the first direction; wherein each channel layer (150) comprises a first side (150aa, 150ba) and an opposite second side (150ab, 150bb), the first side arranged in abutment with a topside or an underside of a pair of source and drain prongs (124a, 134a) and the second side (150ab, 150bb) facing a gate prong (144a, 144b).

公开(公告)号：US20230178635A1

公开(公告)日：2023-06-08

申请号：US18074294

申请日：2022-12-02

Applicant: IMEC VZW

Inventor： Aryan Afzalian ,  Julien Ryckaert ,  Naoto Horiguchi ,  Boon Teik Chan

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L21/308 ,  H01L21/322 ,  H01L21/02

CPC classification number: H01L29/66795 ,  H01L29/785 ,  H01L29/0847 ,  H01L29/1033 ,  H01L21/308 ,  H01L21/322 ,  H01L21/0262

Abstract: A method for forming a FET device is provided, the method including: forming a fin structure; while masking the fin structure from a second side of the fin structure opposite a first side of the fin structure: etching each of first and second fin parts laterally from the first side such that a set of source cavities and a set of drain cavities is formed in first non-channel layers in the first fin part and the second fin part, and subsequently, forming a source body and a drain body, each comprising a respective common body portion along the first side and a set of prongs protruding from the respective common body portion into the source and drain cavities, respectively, and abutting the channel layers; and while masking the fin structure from the first side: etching the third fin part laterally from the second side such that a set of gate cavities extending through the third fin part is formed in second non-channel layers, and subsequently, forming a gate body comprising a common gate body portion along the second side and a set of gate prongs protruding from the common gate body portion into the gate cavities.