公开(公告)号：US20220129031A1

公开(公告)日：2022-04-28

申请号：US17520296

申请日：2021-11-05

Applicant: Intel Corporation

Inventor： Vasudevan Srinivasan ,  Krishnakanth V. Sistla ,  Corey D. Gough ,  Ian M. Steiner ,  Nikhil Gupta ,  Vivek Garg ,  Ankush Varma ,  Sujal A. Vora ,  David P. Lerner ,  Joseph M. Sullivan ,  Nagasubramanian Gurumoorthy ,  William J. Bowhill ,  Venkatesh Ramamurthy ,  Chris MacNamara ,  John J. Browne ,  Ripan Das

IPC: G06F1/08 ,  G06F1/3203 ,  G06F9/30 ,  G06F9/455 ,  G06F1/324

Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.

公开(公告)号：US10310588B2

公开(公告)日：2019-06-04

申请号：US15296096

申请日：2016-10-18

Applicant: Intel Corporation

Inventor： Ankush Varma ,  Krishnakanth V. Sistla ,  Allen W. Chu ,  Ian M. Steiner

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/3287 ,  G06F1/3293 ,  G06F1/3296 ,  G06F9/48

Abstract: In an embodiment, a processor includes a plurality of cores each to independently execute instructions, a power delivery logic coupled to the plurality of cores, and a power controller including a first logic to cause a first core to enter into a first low power state of an operating system power management scheme independently of the OS, during execution of at least one thread on the first core. Other embodiments are described and claimed.

公开(公告)号：US20180181474A1

公开(公告)日：2018-06-28

申请号：US15388146

申请日：2016-12-22

Applicant: Intel Corporation

Inventor： Eric J. DeHaemer ,  Arijit Biswas ,  Reid J. Riedlinger ,  Ian M. Steiner

IPC: G06F11/20

CPC classification number: G06F11/2028 ,  G06F11/2041 ,  G06F11/2043

Abstract: A multicore processor may include multiple processing cores that were previously designated as active cores and at least one processing core that was previously designated as a functional spare. The processor may include an interface to receive, during operation of the processor in an end-user environment, a request to change the designation of at least one of the processing cores. The processor may be to store, into a desired cores configuration data structure in response to the request, data representing a bitmask that reflects the requested change, and to execute a reset sequence. During the reset sequence, the processor may activate, dependent on the bitmask, a processing core previously designated as a functional spare, or may deactivate, dependent on the bitmask, a processing core previously designated as an active core. The processor may include a predetermined maximum number of active cores and a predetermined minimum number of functional spares.

公开(公告)号：US20160266941A1

公开(公告)日：2016-09-15

申请号：US15162709

申请日：2016-05-24

Applicant: Intel Corporation

Inventor： Krishnakanth V. Sistla ,  Mark Rowland ,  Ankush Varma ,  Ian M. Steiner ,  Matthew Bace ,  Daniel Borkowski ,  Vivek Garg ,  Cagdas Akturan ,  Avinash N. Ananthakrishnan

IPC: G06F9/50 ,  G06F1/32

CPC classification number: G06F9/5094 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/3287 ,  Y02D10/126 ,  Y02D10/171

Abstract: In one embodiment, the present invention includes a multicore processor having a power controller with logic to dynamically switch a power management policy from a power biased policy to a performance biased policy when a utilization of the processor exceeds a threshold level. Thus at low utilizations, reduced power consumption can be realized, while at higher utilizations, greater performance can be realized. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括具有功率控制器的多核处理器，所述功率控制器具有在处理器的利用率超过阈值水平时将功率管理策略从功率偏置策略动态切换到性能偏差策略的逻辑。 因此，在低利用率下，可以实现降低的功率消耗，而在更高的利用率下，可以实现更高的性能。 描述和要求保护其他实施例。

公开(公告)号：US20160147291A1

公开(公告)日：2016-05-26

申请号：US14554384

申请日：2014-11-26

Applicant: Intel Corporation

Inventor： Tessil Thomas ,  Phani Kumar Kandula ,  Ramamurthy Krithivas ,  Howard Chin ,  Ian M. Steiner ,  Vivek Garg

IPC: G06F1/32 ,  G06F1/20

CPC classification number: G06F1/3296 ,  G06F1/206 ,  G06F1/32 ,  G06F1/3206 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/16 ,  Y02D10/172

Abstract: In an embodiment, a processor includes a first chip of a multi-chip package (MCP). The first chip includes at least one core and first chip temperature control (TC) logic to assert a first power adjustment signal at a second chip of the MCP responsive to an indication that a first chip temperature of the first chip exceeds a first threshold. The processor also includes a conduit that includes a bi-directional pin to couple the first chip to the second chip within the MCP. The conduit is to transport the first power adjustment signal from the first chip to the second chip and the first power adjustment signal is to cause an adjustment of a second chip power consumption of the second chip. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括多芯片封装（MCP）的第一芯片。 第一芯片包括至少一个核心和第一芯片温度控制（TC）逻辑，以响应于第一芯片的第一芯片温度超过第一阈值的指示来在MCP的第二芯片处断言第一功率调整信号。 处理器还包括导管，其包括将第一芯片耦合到MCP内的第二芯片的双向引脚。 导管将第一功率调整信号从第一芯片传输到第二芯片，第一功率调整信号将引起第二芯片的第二芯片功率消耗的调整。 描述和要求保护其他实施例。

公开(公告)号：US11703906B2

公开(公告)日：2023-07-18

申请号：US17520296

申请日：2021-11-05

Applicant: Intel Corporation

Inventor： Vasudevan Srinivasan ,  Krishnakanth V. Sistla ,  Corey D. Gough ,  Ian M. Steiner ,  Nikhil Gupta ,  Vivek Garg ,  Ankush Varma ,  Sujal A. Vora ,  David P. Lerner ,  Joseph M. Sullivan ,  Nagasubramanian Gurumoorthy ,  William J. Bowhill ,  Venkatesh Ramamurthy ,  Chris MacNamara ,  John J. Browne ,  Ripan Das

IPC: G06F1/08 ,  G06F1/3203 ,  G06F9/30 ,  G06F9/455 ,  G06F1/324

CPC classification number: G06F1/08 ,  G06F1/3203 ,  G06F1/324 ,  G06F9/30101 ,  G06F9/45558 ,  G06F2009/45591

Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.

公开(公告)号：US20170102752A1

公开(公告)日：2017-04-13

申请号：US15296096

申请日：2016-10-18

Applicant: Intel Corporation

Inventor： Ankush Varma ,  Krishnakanth V. Sistla ,  Allen W. Chu ,  Ian M. Steiner

IPC: G06F1/26 ,  G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/266 ,  G06F1/3293 ,  G06F1/3296 ,  G06F9/4893 ,  Y02D10/122 ,  Y02D10/172 ,  Y02D50/20

Abstract: In an embodiment, a processor includes a plurality of cores each to independently execute instructions, a power delivery logic coupled to the plurality of cores, and a power controller including a first logic to cause a first core to enter into a first low power state of an operating system power management scheme independently of the OS, during execution of at least one thread on the first core. Other embodiments are described and claimed.

公开(公告)号：US09495001B2

公开(公告)日：2016-11-15

申请号：US13972569

申请日：2013-08-21

Applicant: Intel Corporation

Inventor： Ankush Varma ,  Krishnakanth V. Sistla ,  Allen W. Chu ,  Ian M. Steiner

IPC: G06F1/32 ,  G06F9/48

CPC classification number: G06F1/3287 ,  G06F1/266 ,  G06F1/3293 ,  G06F1/3296 ,  G06F9/4893 ,  Y02D10/122 ,  Y02D10/172 ,  Y02D50/20

Abstract: In an embodiment, a processor includes a plurality of cores each to independently execute instructions, a power delivery logic coupled to the plurality of cores, and a power controller including a first logic to cause a first core to enter into a first low power state of an operating system power management scheme independently of the OS, during execution of at least one thread on the first core. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括多个核心，每个核心各自独立地执行指令，耦合到多个核心的功率传递逻辑，以及功率控制器，其包括使第一核心进入第一低功率状态的第一逻辑 在第一核心的至少一个线程的执行期间独立于OS的操作系统电源管理方案。 描述和要求保护其他实施例。

公开(公告)号：US20160004291A1

公开(公告)日：2016-01-07

申请号：US14855553

申请日：2015-09-16

Applicant: Intel Corporation

Inventor： Krishnakanth V. Sistla ,  Jeremy Shrall ,  Stephen H. Gunther ,  Efraim Rotem ,  Alon Naveh ,  Eliezer Weissmann ,  Anil Aggarwal ,  Martin T. Rowland ,  Ankush Varma ,  Ian M. Steiner ,  Matthew Bace ,  Avinash N. Ananthakrishnan ,  Jason Brandt

IPC: G06F1/32

CPC classification number: G06F1/3275 ,  G06F1/266 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3234

Abstract: In one embodiment, the present invention includes a processor having a core and a power controller to control power management features of the processor. The power controller can receive an energy performance bias (EPB) value from the core and access a power-performance tuning table based on the value. Using information from the table, at least one setting of a power management feature can be updated. Other embodiments are described and claimed.

公开(公告)号：US09141426B2

公开(公告)日：2015-09-22

申请号：US13631831

申请日：2012-09-28

Applicant: Intel Corporation

Inventor： Malini K. Bhandaru ,  Matthew M. Bace ,  A Leonard Brown ,  Ian M. Steiner ,  Vivek Garg ,  Eric Dehaemer ,  Scott P. Bobholz

IPC: G06F9/46 ,  G06F9/48 ,  G06F11/34 ,  G06F1/32

CPC classification number: G06F9/4881 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3287 ,  G06F11/3409 ,  G06F2201/865 ,  G06F2201/88 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D10/171

Abstract: A processor is described that includes a processing core and a plurality of counters for the processing core. The plurality of counters are to count a first value and a second value for each of multiple threads supported by the processing core. The first value reflects a number of cycles at which a non sleep state has been requested for the first value's corresponding thread, and, a second value that reflects a number of cycles at which a non sleep state and a highest performance state has been requested for the second value's corresponding thread. The first value's corresponding thread and the second value's corresponding thread being a same thread.

Abstract translation: 描述了一种包括处理核心和用于处理核心的多个计数器的处理器。 多个计数器将对由处理核心支持的多个线程中的每个线程计数第一值和第二值。 第一个值反映已经为第一个值对应的线程请求了非睡眠状态的多个周期，以及反映已经请求非睡眠状态和最高性能状态的周期数的第二个值 第二个值的相应线程。 第一个值的相应线程和第二个值的相应线程是相同的线程。