公开(公告)号：US20170125524A1

公开(公告)日：2017-05-04

申请号：US15405182

申请日：2017-01-12

Applicant: Intel Corporation

Inventor： RAVI PILLARISETTY ,  SANSAPTAK DASGUPTA ,  NITI GOEL ,  VAN H. LE ,  MARKO RADOSAVLJEVIC ,  GILBERT DEWEY ,  NILOY MUKHERJEE ,  MATTHEW V. METZ ,  WILLY RACHMADY ,  JACK T. KAVALIEROS ,  BENJAMIN CHU-KUNG ,  HAROLD W. KENNEL ,  STEPHEN M. CEA ,  ROBERT S. CHAU

IPC: H01L29/10 ,  H01L29/165 ,  H01L29/20 ,  H01L21/762 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/16 ,  H01L29/267

CPC classification number: H01L29/785 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/20 ,  H01L29/267 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7851

Abstract: Ge and III-V channel semiconductor devices having maximized compliance and free surface relaxation and methods of fabricating such Ge and III-V channel semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a semiconductor substrate. The semiconductor fin has a central protruding or recessed segment spaced apart from a pair of protruding outer segments along a length of the semiconductor fin. A cladding layer region is disposed on the central protruding or recessed segment of the semiconductor fin. A gate stack is disposed on the cladding layer region. Source/drain regions are disposed in the pair of protruding outer segments of the semiconductor fin.

公开(公告)号：US20180047839A1

公开(公告)日：2018-02-15

申请号：US15790907

申请日：2017-10-23

Applicant: INTEL CORPORATION

Inventor： RAVI PILLARISETTY ,  JACK T. KAVALIEROS ,  WILLY RACHMADY ,  UDAY SHAH ,  BENJAMIN CHU-KUNG ,  MARKO RADOSAVLJEVIC ,  NILOY MUKHERJEE ,  GILBERT DEWEY ,  BEEN Y. JIN ,  ROBERT S. CHAU

IPC: H01L29/775 ,  B82Y10/00 ,  H01L29/778 ,  H01L29/66 ,  H01L29/267 ,  H01L29/15 ,  H01L29/10 ,  H01L29/06 ,  H01L29/78 ,  H01L21/76 ,  H01L29/51 ,  H01L29/165

CPC classification number: H01L29/775 ,  B82Y10/00 ,  H01L21/76 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/122 ,  H01L29/155 ,  H01L29/165 ,  H01L29/267 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66439 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/66977 ,  H01L29/7782 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851

Abstract: Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.

公开(公告)号：US20160172472A1

公开(公告)日：2016-06-16

申请号：US15043935

申请日：2016-02-15

Applicant: INTEL CORPORATION

Inventor： RAVI PILLARISETTY ,  JACK T. KAVALIEROS ,  WILLY RACHMADY ,  UDAY SHAH ,  BENJAMIN CHU-KUNG ,  MARKO RADOSAVLJEVIC ,  NILOY MUKHERJEE ,  GILBERT DEWEY ,  BEEN Y. JIN ,  ROBERT S. CHAU

IPC: H01L29/775 ,  H01L29/06 ,  H01L29/78 ,  H01L29/15

CPC classification number: H01L29/775 ,  B82Y10/00 ,  H01L21/76 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/155 ,  H01L29/165 ,  H01L29/267 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66439 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/66977 ,  H01L29/7782 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851

Abstract: Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.

Abstract translation: 公开了用于形成非平面锗量子阱结构的技术。 特别地，量子阱结构可以用IV或III-V族半导体材料实现，并且包括锗鳍结构。 在一个示例性情况下，提供了非平面量子阱器件，其包括具有衬底（例如硅上的SiGe或GaAs缓冲器），IV或III-V材料阻挡层（例如，SiGe或GaAs或 AlGaAs），掺杂层（例如，掺杂Δ/调制）和未掺杂的锗量子阱层。 在量子阱结构中形成未掺杂的锗鳍结构，以及沉积在鳍结构上的顶部势垒层。 栅极金属可以跨鳍片结构沉积。 排水/源极区域可以形成在翅片结构的相应端部处。

公开(公告)号：US20160133747A1

公开(公告)日：2016-05-12

申请号：US14978624

申请日：2015-12-22

Applicant: INTEL CORPORATION

Inventor： ANAND MURTHY ,  ROBERT S. CHAU ,  TAHIR GHANI ,  KAIZAD R. MISTRY

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/161 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L29/7848 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7842

Abstract: A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases IDSAT and IDLIN of the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.

公开(公告)号：US20190109281A1

公开(公告)日：2019-04-11

申请号：US16214306

申请日：2018-12-10

Applicant: INTEL CORPORATION

Inventor： BRIAN S. DOYLE ,  KAAN OGUZ ,  CHARLES C. KUO ,  MARK L. DOCZY ,  SATYARTH SURI ,  DAVID L. KENCKE ,  ROBERT S. CHAU ,  ROKSANA GOLIZADEH MOJARAD

IPC: H01L43/08 ,  H01L43/12 ,  H01L27/22 ,  G11C11/16

CPC classification number: H01L43/08 ,  G11C11/161 ,  G11C2213/52 ,  H01L27/222 ,  H01L43/12

Abstract: Techniques are disclosed for forming integrated circuit structures including a magnetic tunnel junction (MTJ), such as spin-transfer torque memory (STTM) devices, having magnetic contacts. The techniques include incorporating an additional magnetic layer (e.g., a layer that is similar or identical to that of the magnetic contact layer) such that the additional magnetic layer is coupled antiferromagnetically (or in a substantially antiparallel manner). The additional magnetic layer can help balance the magnetic field of the magnetic contact layer to limit parasitic fringing fields that would otherwise be caused by the magnetic contact layer. The additional magnetic layer may be antiferromagnetically coupled to the magnetic contact layer by, for example, including a nonmagnetic spacer layer between the two magnetic layers, thereby creating a synthetic antiferromagnet (SAF). The techniques can benefit, for example, magnetic contacts having magnetic directions that are substantially in-line or substantially in-plane with the layers of the MTJ stack.

公开(公告)号：US20160359108A1

公开(公告)日：2016-12-08

申请号：US15117594

申请日：2014-03-25

Applicant: INTEL CORPORATION

Inventor： PRASHANT MAJHI ,  ELIJAH V. KARPOV ,  UDAY SHAH ,  NILOY MUKHERJEE ,  CHARLES C. KUO ,  RAVI PILLARISETTY ,  BRIAN S. DOYLE ,  ROBERT S. CHAU

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/08 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1683

Abstract: Techniques are disclosed for forming non-planar resistive memory cells, such as non-planar resistive random-access memory (ReRAM or RRAM) cells. The techniques can be used to reduce forming voltage requirements and/or resistances involved (such as the resistance during the low-resistance state) relative to planar resistive memory cells for a given memory cell space. The non-planar resistive memory cell includes a first electrode, a second electrode, and a switching layer disposed between the first and second electrodes. The second electrode may be substantially between opposing portions of the switching layer, and the first electrode may be substantially adjacent to at least two sides of the switching layer, after the non-planar resistive memory cell is formed. In some cases, an oxygen exchange layer (OEL) may be disposed between the switching layer and one of the first and second electrodes to, for example, increase flexibility in incorporating materials in the cell.

Abstract translation: 公开了用于形成诸如非平面电阻随机存取存储器（ReRAM或RRAM）单元的非平面电阻存储器单元的技术。 该技术可以用于相对于给定存储器单元空间的平面电阻存储器单元来减少所形成的电压要求和/或电阻（例如在低电阻状态期间的电阻）。 非平面电阻式存储单元包括第一电极，第二电极和设置在第一和第二电极之间的开关层。 在形成非平面电阻式存储单元之后，第二电极可以基本上位于开关层的相对部分之间，并且第一电极可以基本上与开关层的至少两侧相邻。 在一些情况下，氧交换层（OEL）可以设置在开关层与第一和第二电极中的一个之间，以例如增加在电池中引入材料的灵活性。

公开(公告)号：US20160204207A1

公开(公告)日：2016-07-14

申请号：US14913173

申请日：2013-09-27

Applicant: INTEL CORPORATION

Inventor： HAN WUI THEN ,  SANSAPTAK DASGUPTA ,  MARKO RADOSAVLJEVIC ,  ROBERT S. CHAU ,  SEUNG HOON SUNG ,  SANAZ K. GARDNER

IPC: H01L29/20 ,  H01L29/207 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/786 ,  H01L29/51 ,  H01L29/06

CPC classification number: H01L29/42392 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/0254 ,  H01L21/28264 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66484 ,  H01L29/66522 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/785 ,  H01L29/78681 ,  H01L29/78696

Abstract: Enhancement mode gallium nitride (GaN) semiconductor devices having a composite high-k metal gate stack and methods of fabricating such devices are described. In an example, a semiconductor device includes a gallium nitride (GaN) channel region disposed above a substrate. A gate stack is disposed on the GaN channel region. The gate stack includes a composite gate dielectric layer disposed directly between the GaN channel region and a gate electrode. The composite gate dielectric layer includes a high band gap Group III-N layer, a first high-K dielectric oxide layer, and a second high-K dielectric oxide layer having a higher dielectric constant than the first high-K dielectric oxide layer. Source/drain regions are disposed on either side of the GaN channel region.

Abstract translation: 描述了具有复合高k金属栅叠层的增强模式氮化镓（GaN）半导体器件及其制造方法。 在一个示例中，半导体器件包括设置在衬底上方的氮化镓（GaN）沟道区。 栅叠层设置在GaN沟道区上。 栅极堆叠包括直接设置在GaN沟道区和栅电极之间的复合栅介质层。 复合栅极电介质层包括具有比第一高K电介质氧化物层更高的介电常数的高带隙组III-N层，第一高K电介质氧化物层和第二高K电介质氧化物层。 源/漏区设置在GaN沟道区的两侧。

公开(公告)号：US20180175184A1

公开(公告)日：2018-06-21

申请号：US15576508

申请日：2015-06-26

Applicant: INTEL CORPORATION

Inventor： HAN WUI THEN ,  SANSAPTAK DASGUPTA ,  SANAZ K. GARDNER ,  MARKO RADOSAVLJEVIC ,  SEUNG HOON SUNG ,  ROBERT S. CHAU

IPC: H01L29/778 ,  H01L29/78 ,  H01L29/20

CPC classification number: H01L29/7786 ,  H01L21/76248 ,  H01L29/2003 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/7783 ,  H01L29/78 ,  H01L29/785 ,  H01L29/78681

Abstract: Techniques are disclosed for gallium nitride (GaN) oxide isolation and formation of GaN transistor structures on a substrate. In some cases, the GaN transistor structures can be used for system-on-chip integration of high-voltage GaN front-end radio frequency (RF) switches on a bulk silicon substrate. The techniques can include, for example, forming multiple fins in a substrate, depositing the GaN layer on the fins, oxidizing at least a portion of each fin in a gap below the GaN layer, and forming one or more transistors on and/or from the GaN layer. In some cases, the GaN layer is a plurality of GaN islands, each island corresponding to a given fin. The techniques can be used to form various non-planar isolated GaN transistor architectures having a relatively small form factor, low on-state resistance, and low off-state leakage, in some cases.

公开(公告)号：US20170092846A1

公开(公告)日：2017-03-30

申请号：US15126682

申请日：2014-07-07

Applicant: INTEL CORPORATION

Inventor： BRIAN S. DOYLE ,  KAAN OGUZ ,  CHARLES C. KUO ,  MARK L. DOCZY ,  SATYARTH SURI ,  DAVID L. KENCKE ,  ROBERT S. CHAU ,  ROKSANA GOLIZADEH MOJARAD

IPC: H01L43/08 ,  H01L43/12 ,  G11C11/16

CPC classification number: H01L43/08 ,  G11C11/161 ,  G11C2213/52 ,  H01L27/222 ,  H01L43/12

Abstract: Techniques are disclosed for forming integrated circuit structures including a magnetic tunnel junction (MTJ), such as spin-transfer torque memory (STTM) devices, having magnetic contacts. The techniques include incorporating an additional magnetic layer (e.g., a layer that is similar or identical to that of the magnetic contact layer) such that the additional magnetic layer is coupled antiferromagnetically (or in a substantially antiparallel manner). The additional magnetic layer can help balance the magnetic field of the magnetic contact layer to limit parasitic fringing fields that would otherwise be caused by the magnetic contact layer. The additional magnetic layer may be antiferromagnetically coupled to the magnetic contact layer by, for example, including a nonmagnetic spacer layer between the two magnetic layers, thereby creating a synthetic antiferromagnet (SAF). The techniques can benefit, for example, magnetic contacts having magnetic directions that are substantially in-line or substantially in-plane with the layers of the MTJ stack.

公开(公告)号：US20160359101A1

公开(公告)日：2016-12-08

申请号：US15117605

申请日：2014-03-28

Applicant: INTEL CORPORATION

Inventor： CHARLES C. KUO ,  KAAN OGUZ ,  BRIAN S. DOYLE ,  MARK L. DOCZY ,  DAVID L. KENCKE ,  SATYARTH SURI ,  ROBERT S. CHAU

IPC: H01L43/08 ,  H01L43/12

CPC classification number: H01L43/08 ,  G11C11/161 ,  H01L43/02 ,  H01L43/12

Abstract: Techniques are disclosed for fabricating a self-aligned spin-transfer torque memory (STTM) device with a dot-contacted free magnetic layer. In some embodiments, the disclosed STTM device includes a first dielectric spacer covering sidewalls of an electrically conductive hardmask layer that is patterned to provide an electronic contact for the STTM's free magnetic layer. The hardmask contact can be narrower than the free magnetic layer. The first dielectric spacer can be utilized in patterning the STTM's fixed magnetic layer. In some embodiments, the STTM further includes an optional second dielectric spacer covering sidewalls of its free magnetic layer. The second dielectric spacer can be utilized in patterning the STTM's fixed magnetic layer and may serve, at least in part, to protect the sidewalls of the free magnetic layer from redepositing of etch byproducts during such patterning, thereby preventing electrical shorting between the fixed magnetic layer and the free magnetic layer.

Abstract translation: 公开了用于制造具有点接触自由磁性层的自对准自旋转移转矩存储器（STTM）装置的技术。 在一些实施例中，所公开的STTM装置包括覆盖导电硬掩模层的侧壁的第一介电间隔物，其被图案化以提供用于STTM自由磁性层的电子接触。 硬掩模接触可以比自由磁性层更窄。 第一介电间隔物可用于图案化STTM的固定磁性层。 在一些实施例中，STTM还包括覆盖其自由磁性层的侧壁的任选的第二电介质间隔物。 第二电介质间隔物可以用于图案化STTM的固定磁性层，并且可以至少部分地用于保护自由磁性层的侧壁在这种图案化期间重新沉积蚀刻副产物，从而防止固定磁性层 和自由磁性层。