公开(公告)号：US20250118647A1

公开(公告)日：2025-04-10

申请号：US18988225

申请日：2024-12-19

Applicant: Intel Corporation

Inventor： Srinivas V. PIETAMBARAM ,  Debendra MALLIK ,  Kristof DARMAWIKARTA ,  Ravindranath V. MAHAJAN ,  Rahul N. MANEPALLI

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065

Abstract: An electronic package includes an interposer having an interposer substrate, a cavity that passes into but not through the interposer substrate, a through interposer via (TIV) within the interposer substrate, and an interposer pad electrically coupled to the TIV. The electronic package includes a nested component in the cavity, wherein the nested component includes a component pad coupled to a through-component via. A core via is beneath the nested component, the core via extending from the nested component through the interposer substrate. A die is coupled to the interposer pad by a first interconnect and coupled to the component pad by a second interconnect.

公开(公告)号：US20230245940A1

公开(公告)日：2023-08-03

申请号：US18133868

申请日：2023-04-12

Applicant: Intel Corporation

Inventor： Rahul JAIN ,  Kyu Oh LEE ,  Siddharth K. ALUR ,  Wei-Lun K. JEN ,  Vipul V. MEHTA ,  Ashish DHALL ,  Sri Chaitra J. CHAVALI ,  Rahul N. MANEPALLI ,  Amruthavalli P. ALUR ,  Sai VADLAMANI

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L23/532 ,  H01L23/498

CPC classification number: H01L23/3185 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/0655 ,  H01L23/53295 ,  H01L23/3128 ,  H01L24/06 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/16227 ,  H01L2924/18161 ,  H01L2224/83051 ,  H01L2224/81

Abstract: An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.

公开(公告)号：US20210090946A1

公开(公告)日：2021-03-25

申请号：US16578698

申请日：2019-09-23

Applicant: Intel Corporation

Inventor： Darko GRUJICIC ,  Matthew ANDERSON ,  Adrian BAYRAKTAROGLU ,  Roy DITTLER ,  Benjamin DUONG ,  Tarek A. IBRAHIM ,  Rahul N. MANEPALLI ,  Suddhasattwa NAD ,  Rengarajan SHANMUGAM ,  Marcel WALL

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: Embodiments herein relate to systems, apparatuses, and/or processes directed to a package or a manufacturing process flow for creating a package that uses multiple seeding techniques to fill vias in the package. Embodiments include a first layer of copper seeding coupled with a portion of the boundary surface and a second layer of copper seeding coupled with the boundary surface or the first layer of copper seeding, where the first layer of copper seeding and the second layer of copper seeding have a combined thickness along the boundary surface that is greater than a threshold value.

公开(公告)号：US20240055345A1

公开(公告)日：2024-02-15

申请号：US17886278

申请日：2022-08-11

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Srinivas V. PIETAMBARAM ,  Gang DUAN ,  Suddhasattwa NAD ,  Jeremy D. ECTON ,  Rahul N. MANEPALLI

IPC: H01L23/522 ,  H01L49/02 ,  H01G11/70 ,  H01L23/15

CPC classification number: H01L23/5223 ,  H01L28/40 ,  H01G11/70 ,  H01L23/15

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a substrate, where the substrate comprises glass. In an embodiment, a pillar is over the substrate, and a capacitor is over the pillar. In an embodiment, the capacitor comprises a first conductive layer on the pillar, a dielectric layer over the first conductive layer, and a second conductive layer over the dielectric layer.

公开(公告)号：US20230092740A1

公开(公告)日：2023-03-23

申请号：US17481257

申请日：2021-09-21

Applicant: Intel Corporation

Inventor： Srinivas V. PIETAMBARAM ,  Rahul N. MANEPALLI ,  Ravindra TANIKELLA

IPC: H01L23/498 ,  H01L25/065 ,  H01L23/538 ,  H01L21/48 ,  H01L23/00

Abstract: Embodiments disclosed herein include electronic packages and methods of assembling such electronic packages. In an embodiment, an electronic package comprises a core, where the core comprises glass. In an embodiment, a hole is through a thickness of the core, and a plug fills the hole, where the plug comprises a polymeric material. In an embodiment, first layers are over the core, where the first layers comprise a dielectric material; and second layers are under the core, where the second layers comprise the dielectric material.

公开(公告)号：US20190019691A1

公开(公告)日：2019-01-17

申请号：US16071826

申请日：2016-02-26

Applicant: INTEL CORPORATION

Inventor： Srinivas V. PIETAMBARAM ,  Rahul N. MANEPALLI

IPC: H01L21/48 ,  H01L21/683 ,  H01L23/498

Abstract: Embodiments herein may relate to providing, on a pad coupled with a carrier panel, a sacrificial element. Embodiments may further relate to providing, on the pad, a mold compound, wherein the mold compound is at least partially adjacent to the sacrificial element. Embodiments may further relate to removing, subsequent to the providing of the mold compound, the sacrificial element to form a via in the mold compound to at least partially expose the pad. Other embodiments may be described and/or claimed.

公开(公告)号：US20230361043A1

公开(公告)日：2023-11-09

申请号：US18224504

申请日：2023-07-20

Applicant: Intel Corporation

Inventor： Srinivas V. PIETAMBARAM ,  Rahul N. MANEPALLI

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/5381 ,  H01L23/5385 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/17 ,  H01L25/0655 ,  H01L24/13 ,  H01L2224/73265 ,  H01L2224/73204 ,  H01L2924/1434 ,  H01L2224/92125 ,  H01L23/5383 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2224/48227 ,  H01L2924/15192 ,  H01L2224/131 ,  H01L2224/32225 ,  H01L2224/16113 ,  H01L2224/16227 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/1511 ,  H01L2924/15747 ,  H01L2924/1579

Abstract: Electrical interconnect bridge technology is disclosed. An electrical interconnect bridge can include a bridge substrate formed of a mold compound material. The electrical interconnect bridge can also include a plurality of routing layers within the bridge substrate, each routing layer having a plurality of fine line and space (FLS) traces. In addition, the electrical interconnect bridge can include a via extending through the substrate and electrically coupling at least one of the FLS traces in one of the routing layers to at least one of the FLS traces in another of the routing layers.

公开(公告)号：US20230317614A1

公开(公告)日：2023-10-05

申请号：US17707351

申请日：2022-03-29

Applicant: Intel Corporation

Inventor： Yi YANG ,  Rahul N. MANEPALLI ,  Suddhasattwa NAD ,  Marcel WALL ,  Benjamin DUONG

IPC: H01L23/532 ,  H05K1/03 ,  H05K1/11 ,  H01L21/48

CPC classification number: H01L23/5329 ,  H05K1/036 ,  H05K1/111 ,  H01L23/53228 ,  H01L21/4857 ,  H01L21/486 ,  H05K2201/0145 ,  H05K2201/0195

Abstract: Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a package substrate with a plurality of first layers, where the first layers comprise an organic material. In an embodiment, a trace is embedded in the package substrate, and a second layer is over the trace, where the second layer comprises silicon and nitrogen. In an embodiment, the second layer is chemically bonded to the one of the first layers

公开(公告)号：US20210366860A1

公开(公告)日：2021-11-25

申请号：US16880483

申请日：2020-05-21

Applicant: Intel Corporation

Inventor： Jung Kyu HAN ,  Hongxia FENG ,  Xiaoying GUO ,  Rahul N. MANEPALLI

IPC: H01L23/00 ,  H01L23/538

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate and a bridge substrate embedded in the package substrate. In an embodiment, first pads are over the package substrate, where the first pads have a first pitch, and second pads are over the bridge substrate, where the second pads have a second pitch that is smaller than the first pitch. In an embodiment, a barrier layer is over individual ones of the second pads. In an embodiment, reflown solder is over individual ones of the first pads and over individual ones of the second pads. In an embodiment, a first standoff height of the reflown solder over the first pads is equal to a second standoff height of the reflown solder over the second pads.

公开(公告)号：US20210358872A1

公开(公告)日：2021-11-18

申请号：US17387836

申请日：2021-07-28

Applicant: Intel Corporation

Inventor： Srinivas V. PIETAMBARAM ,  Rahul N. MANEPALLI ,  Kristof Kuwawi DARMAWIKARTA ,  Robert Alan MAY ,  Aleksandar ALEKSOV ,  Telesphor KAMGAING

IPC: H01L23/66 ,  H01L21/56 ,  H01L23/00

Abstract: Semiconductor packages having a die electrically connected to an antenna by a coaxial interconnect are described. In an example, a semiconductor package includes a molded layer between a first antenna patch and a second antenna patch of the antenna. The first patch may be electrically connected to the coaxial interconnect, and the second patch may be mounted on the molded layer. The molded layer may be formed from a molding compound, and may have a stiffness to resist warpage during fabrication and use of the semiconductor package.