公开(公告)号：US11923307B2

公开(公告)日：2024-03-05

申请号：US16902958

申请日：2020-06-16

Applicant: Intel Corporation

Inventor： Bai Nie ,  Gang Duan ,  Omkar G. Karhade ,  Nitin A. Deshpande ,  Yikang Deng ,  Wei-Lun Jen ,  Tarek A. Ibrahim ,  Sri Ranga Sai Boyapati ,  Robert Alan May ,  Yosuke Kanaoka ,  Robin Shea McRee ,  Rahul N. Manepalli

IPC: H01L23/538 ,  H01L21/48

CPC classification number: H01L23/5381 ,  H01L21/4857 ,  H01L23/5383 ,  H01L23/5386

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

公开(公告)号：US11764150B2

公开(公告)日：2023-09-19

申请号：US16502025

申请日：2019-07-03

Applicant: Intel Corporation

Inventor： Sri Chaitra Jyotsna Chavali ,  Tarek Ibrahim ,  Wei-Lun Jen

IPC: H01L23/522 ,  H01L21/768 ,  H01L49/02 ,  H05K1/18 ,  H01L23/48 ,  H01L23/64

CPC classification number: H01L23/5227 ,  H01L21/76877 ,  H01L23/481 ,  H01L23/645 ,  H01L28/10 ,  H05K1/181 ,  H05K2201/1003

Abstract: Embodiments herein describe techniques for a semiconductor device including a package substrate having a core layer. An inductor may include a first coaxial line and a second coaxial line vertically through the core layer, and an interconnect within the package substrate coupling the first coaxial line and the second coaxial line. A first magnetic segment may surround the first coaxial line within the core layer, and a second magnetic segment may surround the second coaxial line within the core layer. In addition, a third magnetic segment may surround the interconnect and be coupled to the first magnetic segment and the second magnetic segment. Other embodiments may be described and/or claimed.

公开(公告)号：US11521931B2

公开(公告)日：2022-12-06

申请号：US16902768

申请日：2020-06-16

Applicant: Intel Corporation

Inventor： Jason M. Gamba ,  Nitin A. Deshpande ,  Mohit Bhatia ,  Omkar G. Karhade ,  Bai Nie ,  Gang Duan ,  Kristof Kuwawi Darmawikarta ,  Wei-Lun Jen

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

公开(公告)号：US20240113049A1

公开(公告)日：2024-04-04

申请号：US17937474

申请日：2022-10-03

Applicant: Intel Corporation

Inventor： Kristof Kuwawi Darmawikarta ,  Cemil S. Geyik ,  Kemal Aygun ,  Tarek A. Ibrahim ,  Wei-Lun Jen ,  Zhiguo Qian ,  Dilan Seneviratne

IPC: H01L23/66 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L23/66 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5383 ,  H01L23/5386 ,  H01L21/486 ,  H01L2223/6616 ,  H01L2223/6627

Abstract: Embodiments of a microelectronic assembly that includes: a package substrate, comprising buildup layers of an organic dielectric material and a plurality of layers of conductive traces in the organic dielectric material, the package substrate having a first surface and a second surface opposite the first surface; and a plurality of integrated circuit (IC) dies coupled to the package substrate on the first side. The plurality of layers of conductive traces comprises a pair of stripline traces or microstrips in one of the layers, the stripline traces or microstrips are surrounded by air gap structures in the organic dielectric material, and the air gap structures are exposed on the first surface.

公开(公告)号：US20210391266A1

公开(公告)日：2021-12-16

申请号：US16902768

申请日：2020-06-16

Applicant: Intel Corporation

Inventor： Jason M. Gamba ,  Nitin A. Deshpande ,  Mohit Bhatia ,  Omkar G. Karhade ,  Bai Nie ,  Gang Duan ,  Kristof Kuwawi Darmawikarta ,  Wei-Lun Jen

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/00

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

公开(公告)号：US10244632B2

公开(公告)日：2019-03-26

申请号：US15447597

申请日：2017-03-02

Applicant: INTEL CORPORATION

Inventor： Li-Sheng Weng ,  Chi-Te Chen ,  Wei-Lun Jen ,  Olivia Chen ,  Yun Ling

IPC: H05K1/18 ,  H01L23/498 ,  H01L21/48 ,  H05K3/34 ,  H05K3/28 ,  H05K1/11

Abstract: A microelectronic structure may be formed comprising a microelectronic package having a plurality of interconnects and a microelectronic substrate including an upper metallization layer and a solder resist structure, wherein the solder resist structure includes a first structure which forms an electrical connection between a first interconnect of the plurality of interconnects of the microelectronic package and the upper metallization layer of the microelectronic substrate, and wherein solder resist structure includes a second structure which prevents second interconnect of the plurality of interconnects of the microelectronic package from making electrical contact with the upper metallization layer.

公开(公告)号：US11769719B2

公开(公告)日：2023-09-26

申请号：US16017671

申请日：2018-06-25

Applicant: Intel Corporation

Inventor： Jonathan Rosch ,  Wei-Lun Jen ,  Cheng Xu ,  Liwei Cheng ,  Andrew Brown ,  Yikang Deng

IPC: H05K1/11 ,  H05K1/18 ,  H01L23/498 ,  H01L21/48 ,  H05K1/02

CPC classification number: H01L23/49838 ,  H01L21/486 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H05K1/111 ,  H05K1/115 ,  H05K1/025 ,  H05K1/18 ,  H05K2201/095 ,  H05K2201/09727 ,  H05K2201/09736 ,  H05K2201/09827

Abstract: Embodiments include a package substrate, a method of forming the package substrate, and a semiconductor package. A package substrate includes a conductive layer in a dielectric, a first trace and a first via pad of the conductive layer having a first thickness, and a second trace and a second via pad of the conductive layer having a second thickness. The second thickness of second trace and second via pad may be greater than the first thickness of the first trace and first via pad. The dielectric may include a first dielectric thickness and a second dielectric thickness, where the second dielectric thickness may be less than the first dielectric thickness. The package substrate may include a third via having a third thickness on the first via pad, and a fourth via having a fourth thickness on the second via pad, wherein the third thickness is greater than the fourth thickness.

公开(公告)号：US20210391263A1

公开(公告)日：2021-12-16

申请号：US16902958

申请日：2020-06-16

Applicant: Intel Corporation

Inventor： Bai Nie ,  Gang Duan ,  Omkar G. Karhade ,  Nitin A. Deshpande ,  Yikang Deng ,  Wei-Lun Jen ,  Tarek A. Ibrahim ,  Sri Ranga Sai Boyapati ,  Robert Alan May ,  Yosuke Kanaoka ,  Robin Shea McRee ,  Rahul N. Manepalli

IPC: H01L23/538 ,  H01L21/48

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

公开(公告)号：US10658198B2

公开(公告)日：2020-05-19

申请号：US16267004

申请日：2019-02-04

Applicant: INTEL CORPORATION

Inventor： Li-Sheng Weng ,  Chi-Te Chen ,  Wei-Lun Jen ,  Olivia Chen ,  Yun Ling

IPC: H01L21/48 ,  H01L23/498 ,  H05K3/34 ,  H05K1/11 ,  H05K1/18 ,  H05K3/28

Abstract: A microelectronic structure may be formed comprising a microelectronic package having a plurality of interconnects and a microelectronic substrate including an upper metallization layer and a solder resist structure, wherein the solder resist structure includes a first structure which forms an electrical connection between a first interconnect of the plurality of interconnects of the microelectronic package and the upper metallization layer of the microelectronic substrate, and wherein solder resist structure includes a second structure which prevents second interconnect of the plurality of interconnects of the microelectronic package from making electrical contact with the upper metallization layer.

公开(公告)号：US20200066830A1

公开(公告)日：2020-02-27

申请号：US16107778

申请日：2018-08-21

Applicant: Intel Corporation

Inventor： Krishna Bharath ,  Wei-Lun Jen ,  Huong Do ,  Amruthavalli Alur

IPC: H01L49/02 ,  H01L23/522 ,  H01L23/64 ,  H01F27/26 ,  H01L23/00

Abstract: A microelectronics package comprises a substrate comprising at least two conductive layers that are separated by a first dielectric. At least one island comprising a magnetic material is embedded within the dielectric between the two conductive layers. An inductor structure extends within a via in the at least one island. The via extends between the two conductive layers. The inductor structure comprises a conductive wall along a sidewall of the via, and wherein the conductive wall surrounds a second dielectric and is electrically coupled to the two conductive layers.