公开(公告)号：US20190065057A1

公开(公告)日：2019-02-28

申请号：US16113804

申请日：2018-08-27

Applicant: Intel Corporation

Inventor： Yogesh B. Wakchaure ,  Xin Guo ,  David J. Pelster ,  Eric L. Hoffman

IPC: G06F3/06 ,  G11C16/20 ,  G11C11/56 ,  G11C16/10 ,  G06F12/02 ,  G11C16/04

CPC classification number: G06F3/061 ,  G06F3/064 ,  G06F3/0655 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F2212/1016 ,  G06F2212/7202 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/20 ,  G11C2211/5641

Abstract: An example apparatus includes a non-volatile memory including a first memory having a first write rate and a second memory having a second write rate, the first write rate greater than the second write rate An example controller is to determine, based on a ratio, a first portion of the data to be written to the first memory, and a second portion of the data to be written to the second memory type, the second portion of the data not included in the first portion of the data.

公开(公告)号：US10109361B1

公开(公告)日：2018-10-23

申请号：US15637481

申请日：2017-06-29

Applicant: Intel Corporation

Inventor： Ali Khakifirooz ,  Pranav Kalavade ,  Rohit S. Shenoy ,  Aliasgar S. Madraswala ,  Donia Sebastian ,  Xin Guo

IPC: G11C16/04 ,  G11C16/34

Abstract: A memory programmer apparatus may include a first-level programmer to program a first-level cell portion of a multi-level memory in a first pass, a coarse programmer to coarse program a second-level cell portion of the multi-level memory in the first pass, wherein the second-level cell portion includes more levels than the first-level cell portion, and a fine programmer to fine program the second-level cell portion of the multi-level memory in a second pass from data programmed in the first-level cell portion in the first pass.

公开(公告)号：US10055137B2

公开(公告)日：2018-08-21

申请号：US15197617

申请日：2016-06-29

Applicant: INTEL CORPORATION

Inventor： Aliasgar S. Madraswala ,  Yogesh B. Wakchaure ,  David B. Carlton ,  Xin Guo ,  Ryan J. Norton

IPC: G06F12/02 ,  G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0688

Abstract: A first type of command is suspended, by a controller of a non-volatile memory device, in response to determining that a second type of command is waiting for execution. The first type of command is split into a plurality of chunks based on a computed criteria. A second type of command is executed in between execution of at least two chunks of the first type of command.

公开(公告)号：US09830093B2

公开(公告)日：2017-11-28

申请号：US14672080

申请日：2015-03-27

Applicant: Intel Corporation

Inventor： Xin Guo ,  Feng Zhu ,  Yogesh B. Wakchaure ,  David J. Pelster

IPC: G06F3/06 ,  G06F12/10 ,  G06F11/10 ,  G11C11/00 ,  G11C16/26 ,  G11C29/52 ,  G11C29/04

CPC classification number: G06F3/0619 ,  G06F3/0655 ,  G06F3/0688 ,  G06F11/108 ,  G11C11/005 ,  G11C16/26 ,  G11C29/52 ,  G11C2029/0411

Abstract: Methods and apparatus related to a rotated planar XOR scheme for Varied-Sector-Size (VSS) enablement in flat indirection systems are described. In one embodiment, non-volatile memory stores user data in a first set of plurality of planes across a plurality of dies and parity data corresponding to the user data in a second set of plurality of planes. The user data in the first set of the plurality of planes across the plurality of dies and the second set of the plurality of planes is rotated to match a mapping of the parity data. Other embodiments are also disclosed and claimed.

公开(公告)号：US09740437B2

公开(公告)日：2017-08-22

申请号：US14672084

申请日：2015-03-27

Applicant: Intel Corporation

Inventor： Neal R. Mielke ,  Mark Anthony Golez ,  David J. Pelster ,  Paul D. Ruby ,  Xin Guo

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0679 ,  G06F3/0616 ,  G06F3/0652 ,  G06F12/0246

Abstract: Methods and apparatus related to a mechanism for quickly adapting garbage collection resource allocation for an incoming I/O (Input/Output) workload are described. In one embodiment, non-volatile memory stores data corresponding to a first workload and a second workload. Allocation of one or more resources in the non-volatile memory is determined based at least in part on a determination of an average validity of one or more blocks, where the one or more candidate bands are to be processed during operation of the first workload or the second workload. Other embodiments are also disclosed and claimed.

公开(公告)号：US09740419B2

公开(公告)日：2017-08-22

申请号：US15419563

申请日：2017-01-30

Applicant: Intel Corporation

Inventor： Yogesh B. Wakchaure ,  Aliasgar Madraswala ,  Pranav Kalavade ,  Xin Guo ,  David Pelster ,  Myron Loewen ,  Feng Zhu ,  Brennan A. Watt

IPC: G11C11/34 ,  G06F3/06 ,  G06F12/0811

CPC classification number: G06F3/0625 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0688 ,  G06F12/0811 ,  G06F2212/283 ,  G11C7/10 ,  G11C11/4096 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/225 ,  G11C2211/5641

Abstract: Methods, apparatus, systems and articles of manufacture to preserve data of a solid state drive during a power loss event are disclosed. An example method includes setting an alternate data cache (PDC1) to a logical AND of a secondary data cache (SDC) and a primary data cache (PDC0). The PDC1 is set to a logical AND of the PDC1 and a first result of a first sense operation. The PDC0 is set to a logical AND of the PDC0 and an inverse value of the PDC1. The PDC1 is set to a logical AND of the SDC and the PDC0. The PDC1 is set to a logical AND of the PDC1 and an inverse value of a second result of a second sense operation. The SDC is set to a logical AND of the SDC and the PDC0. The SDC is set to a logical OR of the SDC or the PDC0. The PDC0 is set to a logical AND of the PDC0 and a third result of a third sensing operation.

公开(公告)号：US20170123946A1

公开(公告)日：2017-05-04

申请号：US14932870

申请日：2015-11-04

Applicant: Intel Corporation

Inventor： Ning Wu ,  Xin Guo ,  Ramkarthik Ganesan ,  Pranav Kalavade ,  Robert Frickey

IPC: G06F11/20

CPC classification number: G06F11/2094 ,  G06F11/141 ,  G06F11/1441 ,  G06F12/0238 ,  G06F12/0804 ,  G06F12/0868 ,  G06F2201/805 ,  G06F2212/1016 ,  G06F2212/1032 ,  G06F2212/1044 ,  G06F2212/1048 ,  G06F2212/214 ,  G06F2212/222 ,  G06F2212/7203 ,  G06F2212/7204 ,  G06F2212/7211 ,  G11C2211/5641

Abstract: Technology for an apparatus is described. The apparatus can include a first non-volatile memory, a second non-volatile memory to have a write access time faster than the first non-volatile memory, and a memory controller. The memory controller can be configured to detect corrupted data in a selected data region in the first non-volatile memory. The selected data region can be associated with an increased risk of data corruption after data is written from the second non-volatile memory to the first non-volatile memory. Uncorrupted data in the second non-volatile memory that corresponds to the corrupted data in the first non-volatile memory can be identified. Data recovery in the first non-volatile memory can be performed by replacing the corrupted data in the first non-volatile memory with uncorrupted data from the second non-volatile memory.

公开(公告)号：US09418000B2

公开(公告)日：2016-08-16

申请号：US14579971

申请日：2014-12-22

Applicant: Intel Corporation

Inventor： Shyam Sunder Raghunathan ,  Iwen Chao ,  Xin Guo ,  Pranav Kalavade ,  Krishna K. Parat ,  Feng Zhu

IPC: G11C16/04 ,  G06F12/02 ,  G11C16/34 ,  G11C16/14 ,  G11C16/26 ,  G11C16/32 ,  G06F11/10 ,  G11C16/10

CPC classification number: G06F12/0246 ,  G06F11/1084 ,  G06F2212/7211 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/32 ,  G11C16/349 ,  G11C16/3495 ,  G11C29/021 ,  G11C29/028

Abstract: Apparatus, systems, and methods to implement dynamic memory management in nonvolatile memory devices are described. In one example, a controller comprises logic to monitor at least one performance parameter of a nonvolatile memory, determine when the at least one performance parameter passes a threshold which indicates a degradation in performance for the nonvolatile memory, and in response to the at least one performance parameter passing the threshold, to modify at least one operational attribute of the nonvolatile memory. Other examples are also disclosed and claimed.

Abstract translation: 描述了在非易失性存储器件中实现动态存储器管理的装置，系统和方法。 在一个示例中，控制器包括用于监视非易失性存储器的至少一个性能参数的逻辑，确定何时至少一个性能参数通过指示非易失性存储器性能下降的阈值，以及响应于该至少一个 性能参数通过阈值，以修改非易失性存储器的至少一个操作属性。 还公开并要求保护其他实例。

公开(公告)号：US09354973B2

公开(公告)日：2016-05-31

申请号：US13798370

申请日：2013-03-13

Applicant: Intel Corporation

Inventor： Yogesh B. Wakchaure ,  Xin Guo ,  Robert E. Frickey

IPC: G06F11/00 ,  G06F11/10

CPC classification number: G06F11/108

Abstract: Data management logic allocates a portion such as a single plane of a respective multi-plane non-volatile memory device to store parity information for corresponding data striped across multiple planes of multiple non-volatile memory devices. According to one configuration, the data management logic as discussed herein generates parity data based on (a data stripe of) non-parity data stored in multiple planes of multiple different memory devices. The data management logic stores the parity data in the storage plane allocated to store the parity information. Additional configurations include: reserving a parity block amongst multiple non-parity data blocks to store parity data and reserving a parity page amongst multiple non-parity data pages to store parity data.

Abstract translation: 数据管理逻辑分配诸如相应的多平面非易失性存储器设备的单个平面的部分以存储用于在多个非易失性存储器设备的多个平面上条带化的相应数据的奇偶校验信息。 根据一种配置，本文所讨论的数据管理逻辑基于存储在多个不同存储器件的多个平面中的非奇偶校验数据（的数据条带）生成奇偶校验数据。 数据管理逻辑将奇偶校验数据存储在分配用于存储奇偶校验信息的存储平面中。 其他配置包括：在多个非奇偶校验数据块之间保留奇偶校验块以存储奇偶校验数据并且在多个非奇偶校验数据页之间保留奇偶校验页以存储奇偶校验数据。

公开(公告)号：US09298552B2

公开(公告)日：2016-03-29

申请号：US14040554

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Lark-Hoon Leem ,  Xin Guo ,  Ravi H. Motwani ,  Rosanna Yee ,  Scott E. Nelson

IPC: H03M13/00 ,  G06F11/14 ,  G06F11/10

CPC classification number: G06F11/141 ,  G06F11/1012

Abstract: Provided are an apparatus, system, and method for performing an error recovery operation with respect to a read of a block of memory cells in a storage device. A current iteration of a decoding operation is performed by applying at least one reference voltage for the current iteration to a block of the memory cells in the storage device to determine current read values in response to applying the reference voltage. A symbol is generated for each of the read memory cells by combining the determined current read value with at least one value saved during the previous iteration. The symbols are used to determine bit reliability metrics for the block of memory cells. The bit reliability metrics are decoded. In response to the decoding failing, an additional iteration of the decoding operation is performed.

Abstract translation: 提供了一种用于对存储装置中的存储单元块的读取执行错误恢复操作的装置，系统和方法。 通过对当前迭代中的至少一个参考电压施加到存储装置中的存储器单元的块来执行解码操作的当前迭代，以响应于施加参考电压来确定当前读取值。 通过将确定的当前读取值与在先前迭代中保存的至少一个值组合，为每个读取的存储器单元生成符号。 这些符号用于确定存储器单元块的位可靠性度量。 比特可靠性度量被解码。 响应于解码失败，执行解码操作的附加迭代。