公开(公告)号：US20180069141A1

公开(公告)日：2018-03-08

申请号：US15812673

申请日：2017-11-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： STEPHEN W. BEDELL ,  BAHMAN HEKMATSHOARTABARI ,  DEVENDRA K. SADANA ,  GHAVAM G. SHAHIDI ,  DAVOOD SHAHRJERDI

IPC: H01L31/0465 ,  H01L31/20 ,  H01L31/046 ,  H01L31/18 ,  H01L31/0475 ,  H01L31/05 ,  H01L31/076 ,  H01L31/0224 ,  H01L31/077 ,  H01L31/0747 ,  H01L31/075 ,  H01L31/0463 ,  H01L31/068

CPC classification number: H01L31/0465 ,  H01L31/022466 ,  H01L31/046 ,  H01L31/0463 ,  H01L31/0475 ,  H01L31/0504 ,  H01L31/0684 ,  H01L31/0747 ,  H01L31/075 ,  H01L31/076 ,  H01L31/077 ,  H01L31/1876 ,  H01L31/1888 ,  H01L31/1896 ,  H01L31/204 ,  H01L31/208 ,  Y02E10/50

Abstract: A method for fabricating a device with integrated photovoltaic cells includes supporting a semiconductor substrate on a first handle substrate and doping the semiconductor substrate to form doped alternating regions with opposite conductivity. A doped layer is formed over a first side the semiconductor substrate. A conductive material is patterned over the doped layer to form conductive islands such that the conductive islands are aligned with the alternating regions to define a plurality of photovoltaic cells connected in series on a monolithic structure.

公开(公告)号：US20190391681A1

公开(公告)日：2019-12-26

申请号：US16014408

申请日：2018-06-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： BAHMAN HEKMATSHOARTABARI

IPC: G06F3/044 ,  G06F1/16 ,  G06F3/0354

Abstract: A capacitive touch-sensing device includes a substrate and a plurality of configurable resonant circuits. Each configurable resonant circuit includes at least one respective touch capacitor electrode and at least one inductor. The electrodes of the plurality of resonant circuits are distributed on the substrate, and the at least one inductor is a thin film inductor.

公开(公告)号：US20180212094A1

公开(公告)日：2018-07-26

申请号：US15927243

申请日：2018-03-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： TZE-CHIANG CHEN ,  BAHMAN HEKMATSHOARTABARI ,  DEVENDRA K. SADANA ,  DAVOOD SHAHRJERDI

IPC: H01L31/20 ,  H01L31/0747 ,  H01L31/0216 ,  H01L31/0224

CPC classification number: H01L31/202 ,  H01L31/02167 ,  H01L31/022441 ,  H01L31/0747 ,  Y02E10/50

Abstract: A photovoltaic device includes a crystalline substrate having a first dopant conductivity, an interdigitated back contact and a front surface field structure. The front surface field structure includes a crystalline layer formed on the substrate and a noncrystalline layer formed on the crystalline layer. The crystalline layer and the noncrystalline layer are doped with dopants having an opposite dopant conductivity from that of the substrate. Methods are also disclosed.

公开(公告)号：US20170213736A1

公开(公告)日：2017-07-27

申请号：US15483273

申请日：2017-04-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： JOEL P. de SOUZA ,  BAHMAN HEKMATSHOARTABARI ,  JEEHWAN KIM ,  SIEGFRIED L. MAURER ,  DEVENDRA K. SADANA

IPC: H01L21/283 ,  H01L29/66 ,  H01L29/40 ,  H01L21/3213 ,  H01L29/08

CPC classification number: H01L21/283 ,  A23C9/123 ,  A23C9/1315 ,  A23C11/08 ,  H01L21/2254 ,  H01L21/28114 ,  H01L21/30604 ,  H01L21/3213 ,  H01L21/32131 ,  H01L21/32133 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/42376 ,  H01L29/66446 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/78

Abstract: A method for forming a semiconductor device includes patterning a gate conductor, formed on a substrate, and a two-dimensional material formed on the gate conductor. Recesses are formed adjacent to the gate conductor in the substrate, and a doped layer is deposited in the recesses and over a top of the two-dimensional material. Tape is adhered to the doped layer on top of the two-dimensional material. The tape is removed to exfoliate the doped layer from the top of the two-dimensional material to form source and drain regions in the recesses.

公开(公告)号：US20160322481A1

公开(公告)日：2016-11-03

申请号：US15206725

申请日：2016-07-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： KEVIN K. CHAN ,  BAHMAN HEKMATSHOARTABARI ,  TAK H. NING

IPC: H01L29/735 ,  H01L29/08 ,  H01L29/165 ,  H01L29/66 ,  H01L29/205 ,  H01L29/06 ,  H01L29/737 ,  H01L21/02 ,  H01L29/10 ,  H01L29/15

CPC classification number: H01L29/735 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/0649 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/155 ,  H01L29/161 ,  H01L29/165 ,  H01L29/205 ,  H01L29/66242 ,  H01L29/6625 ,  H01L29/737 ,  H01L29/7378

Abstract: A lateral bipolar junction transistor including a base region on a dielectric substrate layer. The base region includes a layered stack of alternating material layers of a first lattice dimension semiconductor material and a second lattice dimension semiconductor material. The first lattice dimension semiconductor material is different from the second lattice dimension semiconductor material to provide a strained base region. A collector region is present on the dielectric substrate layer in contact with a first side of the base region. An emitter region is present on the dielectric substrate in contact with a second side of the base region that is opposite the first side of the base region.

公开(公告)号：US20160204234A1

公开(公告)日：2016-07-14

申请号：US15074633

申请日：2016-03-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： KEVIN K. CHAN ,  BAHMAN HEKMATSHOARTABARI ,  TAK H. NING

IPC: H01L29/735 ,  H01L29/10 ,  H01L29/167 ,  H01L29/08

CPC classification number: H01L29/0638 ,  H01L27/06 ,  H01L27/0623 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/167 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/66234 ,  H01L29/6625 ,  H01L29/66272 ,  H01L29/66287 ,  H01L29/732 ,  H01L29/735 ,  H01L29/7398

Abstract: A method for forming a bipolar junction transistor includes forming a collector intrinsic region, an emitter intrinsic region and an intrinsic base region between the collector intrinsic region and the emitter intrinsic region. A collector extrinsic contact region is formed in direct contact with the collector intrinsic region; an emitter extrinsic contact region is formed on the emitter intrinsic region and a base extrinsic contact region is formed in direct contact with the intrinsic base region. Carbon is introduced into at least one of the collector extrinsic contact region, the emitter extrinsic contact region and the base extrinsic contact region to suppress diffusion of dopants into the junction region.

公开(公告)号：US20150318416A1

公开(公告)日：2015-11-05

申请号：US14798248

申请日：2015-07-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： BAHMAN HEKMATSHOARTABARI ,  ALI KHAKIFIROOZ ,  GHAVAM G. SHAHIDI ,  DAVOOD SHAHRJERDI

IPC: H01L31/0236 ,  H01L31/0352 ,  H01L31/0725

CPC classification number: H01L31/02363 ,  H01L31/03529 ,  H01L31/0725 ,  Y02E10/50

Abstract: A method for forming a multi-junction photovoltaic device includes providing a germanium layer and etching pyramidal shapes in the germanium layer such that (111) facets are exposed to form a textured surface. A first p-n junction is formed on or over the textured surface from III-V semiconductor materials. Another p-n junction is formed over the first p-n junction from III-V semiconductor materials and follows the textured surface.

Abstract translation: 一种用于形成多结光伏器件的方法包括提供锗层并在锗层中蚀刻金字塔形，使得（111）面被暴露以形成纹理表面。 在III-V半导体材料的纹理表面上或上方形成第一p-n结。 在III-V半导体材料的第一个p-n结上形成另一个p-n结，并跟随纹理表面。

公开(公告)号：US20140191237A1

公开(公告)日：2014-07-10

申请号：US13967128

申请日：2013-08-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： BAHMAN HEKMATSHOARTABARI ,  NING LI ,  DEVENDRA K. SADANA ,  DAVOOD SHAHRJERDI

IPC: H01L29/786

CPC classification number: H01L29/66742 ,  H01L29/66772 ,  H01L29/786 ,  H01L29/78654 ,  H01L29/78675 ,  H01L33/0041

Abstract: A method for forming a thin film transistor includes joining a crystalline substrate to an insulating substrate. A doped layer is deposited on the crystalline substrate, and the doped layer is patterned to form source and drain regions. The crystalline substrate is patterned to form an active area such that a conductive channel is formed in the crystalline substrate between the source and drain regions. A gate stack is formed between the source and drain regions, and contacts are formed to the source and drain regions and the gate stack through a passivation layer.

Abstract translation: 一种形成薄膜晶体管的方法，包括将晶体衬底接合到绝缘衬底上。 掺杂层沉积在晶体衬底上，并且掺杂层被图案化以形成源区和漏区。 将晶体衬底图案化以形成有源区，使得在源区和漏区之间的晶体衬底中形成导电沟道。 在源极和漏极区域之间形成栅极堆叠，并且通过钝化层将触点形成到源极和漏极区域以及栅极堆叠。

公开(公告)号：US20140087513A1

公开(公告)日：2014-03-27

申请号：US13657140

申请日：2012-10-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： TZE-CHIANG CHEN ,  BAHMAN HEKMATSHOARTABARI ,  DEVENDRA K. SADANA ,  DAVOOD SHAHRJERDI

IPC: H01L31/0376 ,  H01L31/0368 ,  H01L31/02

CPC classification number: H01L31/022458 ,  H01L31/028 ,  H01L31/03682 ,  H01L31/03762 ,  H01L31/056 ,  H01L31/068 ,  H01L31/0682 ,  H01L31/0684 ,  H01L31/0747 ,  H01L31/1804 ,  Y02E10/50 ,  Y02E10/52 ,  Y02E10/546 ,  Y02E10/547 ,  Y02P70/521

Abstract: A photovoltaic device and method include a crystalline substrate and an emitter contact portion formed in contact with the substrate. A back-surface-field junction includes a homogeneous junction layer formed in contact with the crystalline substrate and having a same conductivity type and a higher active doping density than that of the substrate. The homogeneous junction layer includes a thickness less than a diffusion length of minority carriers in the homogeneous junction layer. A passivation layer is formed in contact with the homogeneous junction layer opposite the substrate, which is either undoped or has the same conductivity type as that of the substrate.

公开(公告)号：US20200058811A1

公开(公告)日：2020-02-20

申请号：US16661413

申请日：2019-10-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  King Abdulaziz City for Science and Technology

Inventor： ABDULRAHMAN M. ALBADRI ,  BAHMAN HEKMATSHOARTABARI ,  DEVENDRA K. SADANA ,  KATHERINE L. SAENGER

IPC: H01L31/0224 ,  H01L31/18 ,  H01L31/0747

Abstract: A method for forming a photovoltaic device includes forming a doped layer on a crystalline substrate, the doped layer having an opposite dopant conductivity as the substrate. A non-crystalline transparent conductive electrode (TCE) layer is formed on the doped layer at a temperature less than 150 degrees Celsius. The TCE layer is flash annealed to crystallize material of the TCE layer at a temperature above about 150 degrees Celsius for less than 10 seconds.