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    SCALABLE RUNTIME VALIDATION FOR ON-DEVICE DESIGN RULE CHECKS
    2.
    发明申请
    SCALABLE RUNTIME VALIDATION FOR ON-DEVICE DESIGN RULE CHECKS 有权

    公开(公告)号：US20230089869A1

    公开(公告)日：2023-03-23

    申请号：US18070655

    申请日：2022-11-29

    申请人： Intel Corporation

    发明人： Furkan Turan ,  Patrick Koeberl ,  Alpa Trivedi ,  Steffen Schulz ,  Scott Weber

    IPC分类号： G06F21/85 ,  G06F30/398 ,  G06N3/04 ,  H04L9/08 ,  G06F9/30 ,  G06F9/50 ,  G06F15/177 ,  G06F15/78 ,  H04L9/40 ,  G06F11/07 ,  G06F30/331 ,  G06F9/38 ,  G06F11/30

    摘要： An apparatus to facilitate scalable runtime validation for on-device design rule checks is disclosed. The apparatus includes a memory to store a contention set, multiplexers, and a validator. In one implementation, the validator is to: receive design rule information for the multiplexers, the design rule information referencing the contention set, wherein the contention set identifies a determined harmful bitstream configuration for each multiplexer instance of the multiplexers, and wherein the contention set comprises a mapping of contents of a user bitstream to configuration bits of the multiplexers; receive, at the validator of the apparatus, the user bitstream for programming the multiplexers of the apparatus; analyze, at the validator using the design rule information, the user bitstream against the contention set at a programming time of the apparatus; and provide an error indication responsive to identifying a match between the user bitstream and the contention set.

    Three Dimensional Circuit Systems And Methods Having Memory Hierarchies
    4.
    发明申请
    Three Dimensional Circuit Systems And Methods Having Memory Hierarchies 有权

    公开(公告)号：US20220405005A1

    公开(公告)日：2022-12-22

    申请号：US17349592

    申请日：2021-06-16

    申请人： Intel Corporation

    发明人： Scott Weber ,  Jawad Khan ,  Ilya Ganusov ,  Martin Langhammer ,  Matthew Adiletta ,  Terence Magee ,  Albert Fazio ,  Richard Coulson ,  Ravi Gutala ,  Aravind Dasu ,  Mahesh Iyer

    IPC分类号： G06F3/06

    摘要： A three dimensional circuit system includes a first integrated circuit die having a core logic region that has first memory circuits and logic circuits. The three dimensional circuit system includes a second integrated circuit die that has second memory circuits. The first and second integrated circuit dies are coupled together in a vertically stacked configuration. The three dimensional circuit system includes third memory circuits coupled to the first integrated circuit die. The third memory circuits reside in a plane of the first integrated circuit die. The logic circuits are coupled to access the first, second, and third memory circuits and data can move between the first, second, and third memories. The third memory circuits have a larger memory capacity and a smaller memory access bandwidth than the second memory circuits. The second memory circuits have a larger memory capacity and a smaller memory access bandwidth than the first memory circuits.

    SCALABLE RUNTIME VALIDATION FOR ON-DEVICE DESIGN RULE CHECKS
    5.
    发明申请
    SCALABLE RUNTIME VALIDATION FOR ON-DEVICE DESIGN RULE CHECKS 有权

    公开(公告)号：US20210110099A1

    公开(公告)日：2021-04-15

    申请号：US17132306

    申请日：2020-12-23

    申请人： Intel Corporation

    发明人： Furkan Turan ,  Patrick Koeberl ,  Alpa Trivedi ,  Steffen Schulz ,  Scott Weber

    IPC分类号： G06F30/398

    摘要： An apparatus to facilitate scalable runtime validation for on-device design rule checks is disclosed. The apparatus includes a memory to store a contention set, one or more multiplexors, and a validator communicably coupled to the memory. In one implementation, the validator is to: receive design rule information for the one or more multiplexers, the design rule information referencing the contention set; analyze, using the design rule information, a user bitstream against the contention set at a programming time of the apparatus, the user bitstream for programming the one or more multiplexors; and provide an error indication responsive to identifying a match between the user bitstream and the contention set.

    Three Dimensional Programmable Logic Circuit Systems And Methods
    8.
    发明申请
    Three Dimensional Programmable Logic Circuit Systems And Methods 有权

    公开(公告)号：US20210313988A1

    公开(公告)日：2021-10-07

    申请号：US17354473

    申请日：2021-06-22

    申请人： Intel Corporation

    发明人： Scott Weber ,  Aravind Dasu ,  Ravi Gutala ,  Mahesh Iyer ,  Eriko Nurvitadhi ,  Archanna Srinivasan ,  Sean Atsatt ,  James Ball

    IPC分类号： H03K19/17736 ,  H03K19/1776 ,  H03K19/17768 ,  H01L25/18

    摘要： A three dimensional circuit system includes first and second integrated circuit (IC) dies. The first IC die includes programmable logic circuits arranged in sectors and first programmable interconnection circuits having first router circuits. The second IC die includes non-programmable circuits arranged in regions and second programmable interconnection circuits having second router circuits. Each of the regions in the second IC die is vertically aligned with at least one of the sectors in the first IC die. Each of the second router circuits is coupled to one of the first router circuits through a vertical die-to-die connection. The first and second programmable interconnection circuits are programmable to route signals between the programmable logic circuits and the non-programmable circuits through the first and second router circuits. The circuit system may include additional IC dies. The first and second IC dies and any additional IC dies are coupled in a vertically stacked configuration.

    Supply Voltage Control Systems And Methods For Integrated Circuits
    9.
    发明申请
    Supply Voltage Control Systems And Methods For Integrated Circuits 有权

    公开(公告)号：US20210311537A1

    公开(公告)日：2021-10-07

    申请号：US17351747

    申请日：2021-06-18

    申请人： Intel Corporation

    发明人： Archanna Srinivasan ,  Ravi Gutala ,  Scott Weber ,  Aravind Dasu ,  Mahesh Iyer ,  Eriko Nurvitadhi

    IPC分类号： G06F1/28 ,  H01L25/065 ,  G05F1/66 ,  H03K19/00

    摘要： A circuit system includes a power control circuit that generates multiple voltage identifiers. Multiple voltage regulator circuits generate multiple supply voltages based on the voltage identifiers. The supply voltages are provided to multiple integrated circuit dies. The power control circuit varies the voltage identifiers based on changes in metrics associated with the integrated circuit dies to cause the voltage regulator circuits to vary the supply voltages. Integrated circuit dies receive supply voltages from voltage regulator circuits through power delivery networks. The integrated circuit dies provide voltage sense signals that indicates the supply voltages. The voltage regulator circuits adjust the supply voltages based on the voltage sense signals to compensate for voltage drops in the power delivery networks.

    Configurable Storage Circuits And Methods
    10.
    发明公开
    Configurable Storage Circuits And Methods 审中-公开

    公开(公告)号：US20240337692A1

    公开(公告)日：2024-10-10

    申请号：US18746853

    申请日：2024-06-18

    申请人： Intel Corporation

    发明人： Rajiv Kumar ,  Amit Agarwal ,  Steven Hsu ,  Scott Weber

    IPC分类号： G01R31/3185

    CPC分类号： G01R31/318541 ,  G01R31/318572

    摘要： A flip-flop circuit includes first and second storage circuits. The flip-flop circuit is configurable to store first values of a data signal in the first storage circuit in response to rising edges of a clock signal and to store second values of the data signal in the second storage circuit in response to falling edges of the clock signal during a double edge triggered mode. The flip-flop circuit is configurable to store third values of the data signal in the first storage circuit and to output the third values from the first storage circuit in response to the clock signal during a single edge triggered mode.