摘要:
A method of patterning and releasing chemically sensitive low k films without the complication of a permanent hardmask stack, yielding an unaltered free-standing structure is provided. The method includes providing a structure including a Si-containing substrate having in-laid etch stop layers located therein; forming a chemically sensitive low k film and a protective hardmask having a pattern atop the structure; transferring the pattern to the chemically sensitive low k film to provide an opening that exposes a portion of the Si-containing substrate; and etching the exposed portion of the Si-containing substrate through the opening to provide a cavity in the Si-containing substrate in which a free-standing low k film structure is formed, while removing the hardmask. In accordance with the present invention, the etching comprises a XeF2 etch gas.
摘要翻译:提供了图案化和释放化学敏感性低k膜的方法,而不需要永久性硬掩模堆叠的复杂性,产生未改变的独立结构。 该方法包括提供包括其中位于其中的内置蚀刻停止层的含Si衬底的结构; 形成化学敏感的低k膜和在结构顶部具有图案的保护性硬掩模; 将图案转移到化学敏感的低k膜上以提供暴露一部分含Si衬底的开口; 并且通过所述开口蚀刻含Si衬底的暴露部分,以在去除硬掩模的同时在其中形成独立的低k膜结构的含Si衬底中提供空腔。 根据本发明,蚀刻包括XeF 2 N 2蚀刻气体。
摘要:
Disclosed are a method and a system for processing a semiconductor structure of the type including a substrate, a dielectric layer, and a TaN—Ta liner on the dielectric layer. The method comprises the step of using XeF2 to remove at least a portion of the TaN—Ta liner completely to the dielectric layer. In the preferred embodiments, the present invention uses XeF2 selective gas phase etching as alternatives to Ta—TaN Chemical Mechanical Polishing (CMP) as a basic “liner removal process” and as a “selective cap plating base removal process.” In this first use, XeF2 is used to remove the metal liner, TaN—Ta, after copper CMP. In the second use, the XeF2 etch is used to selectively remove a plating base (TaN—Ta) that was used to form a metal cap layer over the copper conductor.
摘要:
Disclosed are a method and a system for processing a semiconductor structure of the type including a substrate, a dielectric layer, and a TaN—Ta liner on the dielectric layer. The method comprises the step of using XeF2 to remove at least a portion of the TaN—Ta liner completely to the dielectric layer. In the preferred embodiments, the present invention uses XeF2 selective gas phase etching as alternatives to Ta—TaN Chemical Mechanical Polishing (CMP) as a basic “liner removal process” and as a “selective cap plating base removal process.” In this first use, XeF2 is used to remove the metal liner, TaN—Ta, after copper CMP. In the second use, the XeF2 etch is used to selectively remove a plating base (TaN—Ta) that was used to form a metal cap layer over the copper conductor.
摘要:
Disclosed are a method and a system for processing a semiconductor structure of the type including a substrate, a dielectric layer, and a TaN—Ta liner on the dielectric layer. The method comprises the step of using XeF2 to remove at least a portion of the TaN—Ta liner completely to the dielectric layer. In the preferred embodiments, the present invention uses XeF2 selective gas phase etching as alternatives to Ta—TaN Chemical Mechanical Polishing (CMP) as a basic “liner removal process” and as a “selective cap plating base removal process.” In this first use, XeF2 is used to remove the metal liner, TaN—Ta, after copper CMP. In the second use, the XeF2 etch is used to selectively remove a plating base (TaN—Ta) that was used to form a metal cap layer over the copper conductor.
摘要:
Integrated circuit-chip hot spot temperatures are reduced by providing localized regions of higher thermal conductivity in the conductive material interface at pre-designed locations by controlling how particles in the thermal paste stack- or pile-up during the pressing or squeezing of excess material from the interface. Nested channels are used to efficiently decrease the thermal resistance in the interface, by both allowing for the thermally conductive material with a higher particle volumetric fill to be used and by creating localized regions of densely packed particles between two surfaces.
摘要:
A micro-electromechanical device or MEMS having a conformal layer of material deposited by atomic layer deposition is discussed. The layer may provide physical protection to moving components of the device, may insulate electrical components of the device, may present a biocompatible surface interface to a biological system, and may otherwise improve such devices. The layer may also comprise a combination of multiple materials each deposited with great control to allow creating layers of customizable properties and to allow creating layers having multiple independent functions, such as providing physical protection from wear and providing electrical insulation.
摘要:
A metal inter-diffusion bonding method for forming hermetically sealed wafer-level packaging for MEMS devices. A stack of a first metal is provided on a surface of both a first wafer and a second wafer, the first metal being susceptible to oxidation in air; providing a layer of a second metal, having a melting point lower than that of the first metal, on an upper surface of each stack of the first metal, the layer of second metal being sufficiently thick to inhibit oxidation of the upper surface of the first metal; bringing the layer of the second metal on the first wafer into contact with the layer of second metal on the second wafer to form a bond interface; and applying a bonding pressure to the first and second wafers at a bonding temperature lower than the melting point of the second metal to initiate a bond, the bonding pressure being sufficient to deform the layers of the second metal at the bond interface.