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    EEPROM array with narrow margin of voltage thresholds after erase
    1.
    发明授权
    EEPROM array with narrow margin of voltage thresholds after erase 失效
    擦除后具有电压阈值边缘窄的EEPROM阵列

    公开(公告)号：US5313427A

    公开(公告)日：1994-05-17

    申请号：US763105

    申请日：1991-09-20

    申请人： John F. Schreck ,  David J. McElroy ,  Pradeep L. Shah

    发明人： John F. Schreck ,  David J. McElroy ,  Pradeep L. Shah

    IPC分类号： H01L21/8247 ,  G11C16/02 ,  G11C16/16 ,  H01L27/115 ,  G11C16/06 ,  G11C11/34

    CPC分类号： G11C16/16

    摘要： A nonvolatile memory has pairs of cells in which each cell includes a control gate, a floating gate and a source/drain diffusion. A first cell in each of the pairs is producible to have one value of floating-gate to diffusion capacitance. A second cell in each of the pairs is producible to have a second value of floating-gate to diffusion capacitance different from the first value. The memory includes a first circuit for applying a first erasing pulse to the control gates and the diffusions of the first cells of the pairs and includes a second circuit for applying a second erasing pulse to the control gates and the diffusions of the second cells of the pairs. The first erasing pulse is adjustable to have a different magnitude than the second erasing pulse in order to narrow the margin of erased threshold voltages and thereby compensate for misalignment.

    摘要翻译： 非易失性存储器具有成对的单元，其中每个单元包括控制栅极，浮置栅极和源极/漏极扩散。 每对中的第一个单元可以产生一个浮动栅扩散电容的值。 每对中的第二单元可以产生具有不同于第一值的扩散电容的浮置栅极的第二值。 存储器包括用于将第一擦除脉冲施加到控制栅极的第一电路和对的第一单元的扩散，并且包括用于将第二擦除脉冲施加到控制栅极的第二电路和第二电路的扩散 对。 第一擦除脉冲可调整以具有与第二擦除脉冲不同的幅度，以便缩小擦除阈值电压的余量，从而补偿未对准。

    Method and circuitry for programming floating-gate memory cell using a single low-voltage supply
    2.
    发明授权
    Method and circuitry for programming floating-gate memory cell using a single low-voltage supply 失效
    使用单个低压电源编程浮动栅极存储单元的方法和电路

    公开(公告)号：US5412603A

    公开(公告)日：1995-05-02

    申请号：US239008

    申请日：1994-05-06

    申请人： John F. Schreck ,  Cetin Kaya ,  David J. McElroy

    发明人： John F. Schreck ,  Cetin Kaya ,  David J. McElroy

    IPC分类号： G11C17/00 ,  G11C16/06 ,  G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C7/00

    CPC分类号： G11C16/30 ,  G11C16/12 ,  G11C16/16

    摘要： The drain-to-source voltage and current for programming a selected nonvolatile memory cell 10 are achieved efficiently by pumping the source 11 of a selected cell 11 to a voltage less than the voltage VSS at the reference-voltage terminal of the memory cell array while, at the same time, pumping the drain 12 of the selected cell 10 to a voltage greater than the voltage VCC, which may be 3 V, at the supply-voltage terminal of the memory cell array. The cell substrate W2 is pumped to a voltage close to the voltage of the source 11 and, optionally, below the voltage of the source 11. One or more simple charge-pump circuits convert the output of the voltage supply VCC to a source-drain voltage and current capable of programming the selected nonvolatile cell 10 by hot carrier injection.

    摘要翻译： 通过将所选择的单元11的源极11泵送到小于存储单元阵列的参考电压端子处的电压VSS的电压来有效地实现用于对选定的非易失性存储单元10进行编程的漏极到源极电压和电流，同时 同时，在存储单元阵列的电源电压端将泵浦所选单元10的漏极12的电压大于可以为3V的电压VCC。 电池基板W2被泵浦到接近源极11的电压的电压，并且可选地低于源11的电压。一个或多个简单的电荷泵电路将电压源VCC的输出转换为源极 - 漏极 能够通过热载流子注入对所选择的非易失性电池10进行编程的电压和电流。

    Segmented, multiple-decoder memory array and method for programming a memory array
    3.
    发明授权
    Segmented, multiple-decoder memory array and method for programming a memory array 失效
    分段的多解码器存储器阵列和用于编程存储器阵列的方法

    公开(公告)号：US5313432A

    公开(公告)日：1994-05-17

    申请号：US790122

    申请日：1991-11-12

    申请人： Sung-Wei Lin ,  John F. Schreck ,  Phat C. Truong ,  David J. McElroy ,  Harvey J. Stiegler ,  Benjamin H. Ashmore, Jr. ,  Manzur Gill

    发明人： Sung-Wei Lin ,  John F. Schreck ,  Phat C. Truong ,  David J. McElroy ,  Harvey J. Stiegler ,  Benjamin H. Ashmore, Jr. ,  Manzur Gill

    IPC分类号： G11C5/02 ,  G11C8/12 ,  G11C16/04 ,  G11C16/08 ,  G11C16/12 ,  G11C16/06

    CPC分类号： G11C16/0416 ,  G11C16/08 ,  G11C16/12 ,  G11C5/025 ,  G11C8/12

    摘要： A wordline-decode system of a nonvolatile memory array is split into three smaller decoding subsystems (a Read-Mode Decode Subsystem, a Program/Erase-Mode Decode Subsystem and a Segment-Select Decoder Subsystem). The segmented array has small bitline capacitance and requires few input connections to each decoding subsystem. The Read-Mode Decoder circuitry and the Program/Erase-Mode Decoder circuitry are separated, allowing the Read-Mode Decoder circuitry to be desired for high speed access and allowing the Program/Erase-Mode Decoder circuitry to be desired for high voltage operation. Buried-bitline segment-select transistors reduce the area required for those transistors. Erasing may be performed after first checking each row of a segment to determine the present of any over-erased cells. Programming may be performed by allowing the common source-column lines of the selected segment to float and by placing preselected voltages on the appropriate wordline and drain-column line.

    摘要翻译： 非易失性存储器阵列的字线解码系统被分成三个较小的解码子系统（读模式解码子系统，程序/擦除模式解码子系统和段选择解码器子系统）。 分段阵列具有小的位线电容，并且需要几个输入连接到每个解码子系统。 读模式解码器电路和编程/擦除模式解码器电路分开，允许读模式解码器电路用于高速访问，并允许对高电压操作进行编程/擦除模式解码器电路。 掩埋位线段选择晶体管减少了那些晶体管所需的面积。 可以在首先检查段的每一行以确定任何过度擦除的单元的存在之后执行擦除。 可以通过允许所选段的公共源列线浮动并且将预选的电压放置在适当的字线和漏极 - 列线上来执行编程。

    Nonvolatile memory device having program and/or erase voltage clamp
    4.
    发明授权
    Nonvolatile memory device having program and/or erase voltage clamp 有权
    具有编程和/或擦除电压钳位的非易失性存储器件

    公开(公告)号：US6049483A

    公开(公告)日：2000-04-11

    申请号：US368453

    申请日：1999-08-03

    申请人： John F. Schreck ,  David J. McElroy ,  Brian W. Huber

    发明人： John F. Schreck ,  David J. McElroy ,  Brian W. Huber

    IPC分类号： G11C5/14 ,  G11C16/12 ,  G11C16/14

    CPC分类号： G11C16/14 ,  G11C16/12 ,  G11C5/145

    摘要： Circuits for applying a programming voltage and erase voltage to memory cells in a nonvolatile memory device are disclosed. The reverse breakdown of p-n junctions within the memory cells is prevented by providing a clamping p-n junction in the path used to apply the program or erase voltage to the memory cells. The clamping p-n junction will breakdown before the p-n junctions within the memory cells, protecting the memory cells from the adverse effects of a reverse breakdown condition.

    摘要翻译： 公开了用于向非易失性存储器件中的存储单元施加编程电压和擦除电压的电路。 通过在用于将编程或擦除电压施加到存储器单元的路径中提供钳位p-n结来防止存储器单元内的p-n结的反向击穿。 钳位p-n结将在存储器单元内的p-n结之前击穿，从而保护存储单元不受反向故障条件的不利影响。

    Skewed reference to improve ones and zeros in EPROM arrays
    5.
    发明授权
    Skewed reference to improve ones and zeros in EPROM arrays 失效
    倾斜的参考，以提高EPROM阵列中的零和零

    公开(公告)号：US5287315A

    公开(公告)日：1994-02-15

    申请号：US057435

    申请日：1993-05-07

    申请人： John F. Schreck ,  Debra J. Dolby ,  David J. McElroy ,  Eddie H. Breashears ,  John H. MacPeak

    发明人： John F. Schreck ,  Debra J. Dolby ,  David J. McElroy ,  Eddie H. Breashears ,  John H. MacPeak

    IPC分类号： G11C16/28 ,  G11C29/00 ,  G11C7/02 ,  G11C11/34

    CPC分类号： G11C29/78 ,  G11C16/28

    摘要： A structure and method for improving the sense margin of nonvolatile memories is disclosed. An improvement to the sense margin of nonvolatile memories is accomplished by improving the margin both for "ones" at low control gate voltage Vcc and for "zeros" at high control gate voltage Vcc. Improvement in sensing at low control gate voltages Vcc is accomplished by skewing the sense amplifier response characteristics by forming the channel length of the reference memory cell to have a longer channel length than the memory cells of the array.

    摘要翻译： 公开了一种用于改善非易失性存储器的检测边缘的结构和方法。 通过改善在低控制栅极电压Vcc下的“一个”和在高控制栅极电压Vcc下的“零”的裕度来实现对非易失性存储器的感测边缘的改进。 在低控制栅极电压Vcc下的感测改善通过使参考存储器单元的沟道长度形成具有比阵列的存储单元更长的沟道长度的方式来使读出放大器响应特性偏斜来实现。

    Nonvolatile memory array wordline driver circuit with voltage translator circuit
    9.
    发明授权
    Nonvolatile memory array wordline driver circuit with voltage translator circuit 失效
    具有电压转换电路的非易失性存储器阵列字线驱动电路

    公开(公告)号：US5287536A

    公开(公告)日：1994-02-15

    申请号：US9276

    申请日：1993-01-22

    申请人： John F. Schreck ,  Phat C. Truong ,  Benjamin H. Ashmore, Jr. ,  Harvey J. Steigler

    发明人： John F. Schreck ,  Phat C. Truong ,  Benjamin H. Ashmore, Jr. ,  Harvey J. Steigler

    IPC分类号： G11C16/08 ,  G11C16/12 ,  G11C16/06 ,  G11C5/14

    CPC分类号： G11C16/08 ,  G11C16/12

    摘要： A circuit for driving a wordline or group of wordlines in a floating-gate type EEPROM cell array includes a read-driver subcircuit for switching positive read voltages, a program-driver subcircuit for switching positive programming voltages and, optionally, a subcircuit for switching negative erasing voltages. The read-driver subcircuit may be constructed using relatively short-channel transistors for relatively high speed operation when connected to high-capacitance wordlines. On the other hand, the program-driver subcircuit may be constructed using relatively long-channel transistors and those long-channel transistors may be located on the memory chip remotely from the memory cells and from the read-driver circuit. P channel isolating transistors are used to isolate unused circuitry during operation. A voltage translator in the program-driver subcircuit has a transistor configuration that lessens the probability that the breakdown voltages of those transistors will be exceeded. A method for programming nonvolatile memory cell arrays is also disclosed.

    摘要翻译： 用于驱动浮栅型EEPROM单元阵列中的字线或字线组的电路包括用于切换正读取电压的读取驱动器子电路，用于切换正编程电压的程序驱动器子电路和可选地用于切换负极的子电路 擦除电压。 当连接到高电容字线时，读驱动器子电路可以使用相对较短的沟道晶体管来构造，用于相对高速的操作。 另一方面，程序驱动器子电路可以使用相对长的沟道晶体管构成，并且那些长沟道晶体管可以远离存储器单元和读取驱动器电路位于存储器芯片上。 P沟道隔离晶体管用于在运行期间隔离未使用的电路。 程序驱动器子电路中的电压转换器具有减小超过这些晶体管的击穿电压的可能性的晶体管配置。 还公开了非易失性存储单元阵列的编程方法。

    Threshold/voltage detection circuit
    10.
    发明授权
    Threshold/voltage detection circuit 失效
    阈值/电压检测电路

    公开(公告)号：US5278458A

    公开(公告)日：1994-01-11

    申请号：US807545

    申请日：1991-12-13

    申请人： Wayland B. Holland ,  Gary L. Howe ,  John F. Schreck

    发明人： Wayland B. Holland ,  Gary L. Howe ,  John F. Schreck

    IPC分类号： H03K3/3565 ,  H03K17/30 ,  H05K3/01 ,  H05K5/153

    CPC分类号： H03K17/302 ,  H03K3/3565

    摘要： One aspect of the present invention includes a circuit for detecting when an input voltage exceeds a predetermined threshold. The circuit for detecting includes an input for receiving the input voltage. Further, the circuit includes a plurality of switching devices, wherein each of the switching devices comprises a first and second terminal for defining a variable conductive path, and a third terminal for receiving a signal to control said variable conductive path. The plurality of switching devices includes three switching devices. The first switching device has a first terminal coupled to the input and a second terminal coupled to a first node. The second switching device has a first terminal coupled to the first node and a second terminal coupled to a second node. Finally, the third switching device has a first terminal coupled to the second node. Each of the first, second and third switching devices are of like conductivity type, and the second node provides a first voltage if the input voltage is below the predetermined threshold and provides a second voltage if the input voltage is above the predetermined threshold.

    摘要翻译： 本发明的一个方面包括用于检测输入电压何时超过预定阈值的电路。 用于检测的电路包括用于接收输入电压的输入端。 此外，电路包括多个开关装置，其中每个开关装置包括用于限定可变导电路径的第一和第二端子，以及用于接收控制所述可变导电路径的信号的第三端子。 多个开关装置包括三个开关装置。 第一开关装置具有耦合到输入的第一端子和耦合到第一节点的第二端子。 第二交换设备具有耦合到第一节点的第一终端和耦合到第二节点的第二终端。 最后，第三交换设备具有耦合到第二节点的第一终端。 第一，第二和第三开关装置中的每一个具有类似导电类型，如果输入电压低于预定阈值，则第二节点提供第一电压，并且如果输入电压高于预定阈值则提供第二电压。