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    Semiconductor memory device and method of controlling the same
    3.
    发明授权
    Semiconductor memory device and method of controlling the same 有权

    公开(公告)号：US11575395B2

    公开(公告)日：2023-02-07

    申请号：US17317280

    申请日：2021-05-11

    Applicant: Kioxia Corporation

    Inventor： Shinichi Kanno ,  Hironori Uchikawa

    IPC: H03M13/29 ,  G06F11/10 ,  G11C29/52 ,  H03M13/00 ,  H03M13/35 ,  G06F13/16 ,  G06F13/40 ,  H03M13/03

    Abstract: A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.

    Memory system
    4.
    发明授权
    Memory system 有权

    公开(公告)号：US11309918B2

    公开(公告)日：2022-04-19

    申请号：US17005282

    申请日：2020-08-27

    Applicant: KIOXIA CORPORATION

    Inventor： Yuta Kumano ,  Hironori Uchikawa

    IPC: H03M13/00 ,  H03M13/15 ,  G06F11/07 ,  H03M13/11

    Abstract: A memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory stores a multidimensional error correction code in which each of a plurality of symbol groups is encoded by both a first component code and a second component code. The memory controller reads the error correction code from the nonvolatile memory, executes a first decoding process using the first component code and the second component code, and when the first decoding process fails, executes a second decoding process on an error symbol group. The second decoding process includes a process of selecting the positions of a plurality of symbols whose values included in the error symbol group are to be inverted according to a decision rule. The decision rule includes a rule for cyclically shifting a position selected for the second decoding process at to decide the position for the second decoding process at the next time.

    Memory system
    5.
    发明授权
    Memory system 有权

    公开(公告)号：US11025281B2

    公开(公告)日：2021-06-01

    申请号：US16806322

    申请日：2020-03-02

    Applicant: KIOXIA CORPORATION

    Inventor： Naoko Kifune ,  Hironori Uchikawa

    IPC: H03M13/29 ,  H03M13/45 ,  H03M13/11 ,  H03M13/15

    Abstract: A memory system includes a nonvolatile memory and a memory controller that encodes first XOR data generated by performing an exclusive OR operation on pieces of user data, wherein a value of each bit of the XOR data is generated by performing an exclusive OR operation on values of bits that are at one of a plurality of bit positions of a piece of user data, generates codewords by encoding the plurality of pieces of user data and the generated XOR data, respectively, and stores the codewords in the nonvolatile memory. The memory controller also performs a read operation by reading the codewords from the nonvolatile memory and decoding them. When the decoding of two or more of the codewords fails, the memory controller generates second XOR data, and corrects the value of one of the bits corresponding to a codeword whose decoding failed, based on the second XOR data.

    Multidimensional encoding and decoding in memory system
    9.
    发明授权
    Multidimensional encoding and decoding in memory system 有权

    公开(公告)号：US11664822B2

    公开(公告)日：2023-05-30

    申请号：US17680164

    申请日：2022-02-24

    Applicant: KIOXIA CORPORATION

    Inventor： Yuta Kumano ,  Hironori Uchikawa

    IPC: H03M13/00 ,  H03M13/11 ,  H03M13/15 ,  G06F11/10 ,  H03M13/37 ,  H03M13/45

    CPC classification number: H03M13/1111 ,  G06F11/1068 ,  H03M13/1575 ,  H03M13/3723 ,  H03M13/45

    Abstract: A memory system includes an encoder and a decoder. The encoder is configured to generate multi-dimensionally-coded data to be written into the non-volatile memory. Data bits of the multi-dimensionally-coded data are grouped into first and second dimensional codes with respect to first and second dimensions, respectively. The decoder is configured to, with respect to each of the first and second dimensional codes included in read multi-dimensionally-coded data, generate a syndrome value of the dimensional code, generate low-reliability location information, generate a soft-input value based on the syndrome value and the low-reliability location information, decode the dimensional code through correction of the dimensional code using the soft-input value, and store modification information indicating a bit of the dimensional code corrected through the correction and reliability information indicating reliability of the correction. The decoder generates the soft-input value also based on the modification information and the reliability information in the memory.

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