公开(公告)号：US20230397406A1

公开(公告)日：2023-12-07

申请号：US17848107

申请日：2022-06-23

Applicant: Micron Technology, Inc

Inventor： Sau Ha Cheung ,  Soichi Sugiura ,  Jaydip Guha ,  Anthony J. Kanago ,  Richard Beeler

IPC: H01L27/108

CPC classification number: H01L27/10823 ,  H01L27/10876

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a recess formed in a semiconductor material; a dielectric structure formed in the recess; and a control gate for a transistor of a memory cell, the control gate including a first conductive portion formed in the recess and separated from the semiconductor material by a first portion of the dielectric structure, the first dielectric portion including a first dielectric material between the semiconductor material and the second dielectric material, and a second dielectric material between the first dielectric material and the first conductive portion; and the control gate including the second conductive portion formed over the first conductive portion and separated from the semiconductor material by a second portion of the dielectric structure between the semiconductor material and second conductive portion.

公开(公告)号：US20230063549A1

公开(公告)日：2023-03-02

申请号：US17411643

申请日：2021-08-25

Applicant: Micron Technology, Inc.

Inventor： Sau Ha Cheung ,  Soichi Sugiura ,  Jaydip Guha ,  Anthony Kanago ,  Richard Beeler

IPC: H01L29/423 ,  H01L27/108 ,  H01L29/51 ,  H01L29/40

Abstract: A method of forming a recessed access device comprises forming a trench in semiconductor material. Sidewalls and a bottom of the trench are lined with low-k gate-insulator material. The low-k gate-insulator material is characterized by its dielectric constant k being no greater than 4.0. Sacrificial material is formed in a bottom portion of the trench over the low-k gate-insulator material and over the trench bottom. A high-k gate-insulator material is formed in an upper portion of the trench above the sacrificial material and laterally-inward of the low-k gate-insulator material that is in the upper portion of the trench. The high-k gate-insulator material is characterized by its dielectric constant k being greater than 4.0. The sacrificial material is replaced with a conductive gate that has its top above a bottom of the high-k gate-insulator material. A pair of source/drain regions is formed in upper portions of the semiconductor material on opposing lateral sides of the trench. A channel region is in the semiconductor material below the pair of source/drain regions and extends along the trench sidewalls and around the trench bottom. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US20150014766A1

公开(公告)日：2015-01-15

申请号：US14502978

申请日：2014-09-30

Applicant: Micron Technology, Inc.

Inventor： Lars P. Heineck ,  Shyam Surthi ,  Jaydip Guha

IPC: H01L27/108 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L27/10802 ,  H01L21/28132 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10891 ,  H01L29/66666 ,  H01L29/7788 ,  H01L29/7827 ,  H01L29/7841

Abstract: Some embodiments include memory arrays. The memory arrays may have digit lines under vertically-oriented transistors, with the digit lines interconnecting transistors along columns of the array. Each individual transistor may be directly over only a single digit line, with the single digit line being entirely composed of one or more metal-containing materials. The digit lines can be over a deck, and electrically insulative regions can be directly between the digit lines and the deck. Some embodiments include methods of forming memory arrays. A plurality of linear segments of silicon-containing material may be formed to extend upwardly from a base of the silicon-containing material. The base may be etched to form silicon-containing footings under the linear segments, and the footings may be converted into metal silicide. The linear segments may be patterned into a plurality of vertically-oriented transistor pedestals that extend upwardly from the metal silicide footings.

Abstract translation: 一些实施例包括存储器阵列。 存储器阵列可以在垂直取向的晶体管下面具有数字线，数字线将晶体管沿阵列的列互连。 每个单独的晶体管可以直接在单个数字线上，单个数字线完全由一个或多个含金属材料组成。 数字线可以在甲板上，电绝缘区域可以直接位于数字线和甲板之间。 一些实施例包括形成存储器阵列的方法。 可以形成多个含硅材料的线性段，以从含硅材料的基底向上延伸。 基底可以被蚀刻以在线性段下面形成含硅基底，并且基脚可以被转换成金属硅化物。 线性段可以被图案化成从金属硅化物基部向上延伸的多个垂直取向的晶体管基座。

公开(公告)号：US08871589B2

公开(公告)日：2014-10-28

申请号：US14030880

申请日：2013-09-18

Applicant: Micron Technology, Inc.

Inventor： Lars P Heineck ,  Shyam Surthi ,  Jaydip Guha

IPC: H01L29/66 ,  H01L27/108 ,  H01L29/78

CPC classification number: H01L27/10802 ,  H01L21/28132 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10891 ,  H01L29/66666 ,  H01L29/7788 ,  H01L29/7827 ,  H01L29/7841

Abstract: Some embodiments include memory arrays. The memory arrays may have digit lines under vertically-oriented transistors, with the digit lines interconnecting transistors along columns of the array. Each individual transistor may be directly over only a single digit line, with the single digit line being entirely composed of one or more metal-containing materials. The digit lines can be over a deck, and electrically insulative regions can be directly between the digit lines and the deck. Some embodiments include methods of forming memory arrays. A plurality of linear segments of silicon-containing material may be formed to extend upwardly from a base of the silicon-containing material. The base may be etched to form silicon-containing footings under the linear segments, and the footings may be converted into metal silicide. The linear segments may be patterned into a plurality of vertically-oriented transistor pedestals that extend upwardly from the metal silicide footings.

Abstract translation: 一些实施例包括存储器阵列。 存储器阵列可以在垂直取向的晶体管下面具有数字线，数字线将晶体管沿阵列的列互连。 每个单独的晶体管可以直接在单个数字线上，单个数字线完全由一个或多个含金属材料组成。 数字线可以在甲板上，电绝缘区域可以直接位于数字线和甲板之间。 一些实施例包括形成存储器阵列的方法。 可以形成多个含硅材料的线性段，以从含硅材料的基底向上延伸。 基底可以被蚀刻以在线性段下面形成含硅基底，并且基脚可以被转换成金属硅化物。 线性段可以被图案化成从金属硅化物基部向上延伸的多个垂直取向的晶体管基座。

公开(公告)号：US12178033B2

公开(公告)日：2024-12-24

申请号：US17215904

申请日：2021-03-29

Applicant: Micron Technology, Inc.

Inventor： Anthony J. Kanago ,  Jaydip Guha ,  Srinivas Pulugurtha ,  Soichi Sugiura

IPC: G11C11/40 ,  G11C11/4096 ,  G11C29/54 ,  H01L29/786 ,  H10B12/00

Abstract: Some embodiments include apparatuses and methods using the apparatuses. One of the embodiments includes a capacitor, a transistor coupled to the capacitor, the transistor and the capacitor included in a memory cell; the transistor including a channel structure, a gate including a portion located on a side of the channel structure, and a dielectric structure between the channel structure and the gate; and on-die circuitry configured to selectively apply a stress condition to the transistor to tune a threshold voltage of the transistor.

公开(公告)号：US20240074161A1

公开(公告)日：2024-02-29

申请号：US18236579

申请日：2023-08-22

Applicant: Micron Technology, Inc.

Inventor： Russell Allen Benson ,  Shivani Srivastava ,  Jaydip Guha ,  Raghunath Singanamalla

IPC: H10B12/00

CPC classification number: H10B12/485 ,  H10B12/05 ,  H10B12/482

Abstract: A variety of applications can include apparatus having a memory device with digit line contacts disposed in a dielectric and metal digit lines coupled to various of the digit line contacts by at most one metal barrier above the dielectric. Material of the metal digit lines is used as a contact metal to a transistor in a periphery to the memory array region, where the transistor is coupled to the metal contact by multiple barrier metals on polysilicon on the transistor. An integration flow of metallization for periphery devices to a memory array and digit lines can be implemented to allow separate barrier metal formation between the memory array and the periphery, while still using the same material as the main conductor. Barrier metals can be formed for the periphery and the memory array region and then cleared from the memory array region before forming the main conductor.

公开(公告)号：US11626488B2

公开(公告)日：2023-04-11

申请号：US17453621

申请日：2021-11-04

Applicant: Micron Technology, Inc.

Inventor： Srinivas Pulugurtha ,  Jaydip Guha ,  Scott E. Sills ,  Yi Fang Lee

IPC: H01L23/495 ,  H01L29/10 ,  H01L29/24 ,  H01L27/11502 ,  H01L27/06 ,  H01L21/8234 ,  H01L27/108

Abstract: Some embodiments include a transistor having an active region containing semiconductor material. The semiconductor material includes at least one element selected from Group 13 of the periodic table in combination with at least one element selected from Group 16 of the periodic table. The active region has a first region, a third region offset from the first region, and a second region between the first and third regions. A gating structure is operatively adjacent to the second region. A first carrier-concentration-gradient is within the first region, and a second carrier-concentration-gradient is within the third region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US09318493B2

公开(公告)日：2016-04-19

申请号：US14502978

申请日：2014-09-30

Applicant: Micron Technology, Inc.

Inventor： Lars P. Heineck ,  Shyam Surthi ,  Jaydip Guha

IPC: H01L27/108 ,  H01L29/66 ,  H01L29/778 ,  H01L21/28 ,  H01L29/78

CPC classification number: H01L27/10802 ,  H01L21/28132 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10891 ,  H01L29/66666 ,  H01L29/7788 ,  H01L29/7827 ,  H01L29/7841

Abstract: Some embodiments include memory arrays. The memory arrays may have digit lines under vertically-oriented transistors, with the digit lines interconnecting transistors along columns of the array. Each individual transistor may be directly over only a single digit line, with the single digit line being entirely composed of one or more metal-containing materials. The digit lines can be over a deck, and electrically insulative regions can be directly between the digit lines and the deck. Some embodiments include methods of forming memory arrays. A plurality of linear segments of silicon-containing material may be formed to extend upwardly from a base of the silicon-containing material. The base may be etched to form silicon-containing footings under the linear segments, and the footings may be converted into metal silicide. The linear segments may be patterned into a plurality of vertically-oriented transistor pedestals that extend upwardly from the metal silicide footings.

Abstract translation: 一些实施例包括存储器阵列。 存储器阵列可以在垂直取向的晶体管下面具有数字线，数字线将晶体管沿阵列的列互连。 每个单独的晶体管可以直接在单个数字线上，单个数字线完全由一个或多个含金属材料组成。 数字线可以在甲板上，电绝缘区域可以直接位于数字线和甲板之间。 一些实施例包括形成存储器阵列的方法。 可以形成多个含硅材料的线性段，以从含硅材料的基底向上延伸。 基底可以被蚀刻以在线性段下面形成含硅基底，并且基脚可以被转换成金属硅化物。 线性段可以被图案化成从金属硅化物基部向上延伸的多个垂直取向的晶体管基座。

公开(公告)号：US20150206886A1

公开(公告)日：2015-07-23

申请号：US14569337

申请日：2014-12-12

Applicant: Micron Technology, Inc.

Inventor： Jaydip Guha ,  Shyam Surthi

IPC: H01L27/108 ,  H01L29/04 ,  H01L21/324 ,  H01L21/02 ,  H01L21/265 ,  H01L29/66 ,  H01L29/16

CPC classification number: H01L27/10876 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/02598 ,  H01L21/26513 ,  H01L21/324 ,  H01L21/8222 ,  H01L21/8229 ,  H01L21/823487 ,  H01L27/0814 ,  H01L27/0823 ,  H01L27/1021 ,  H01L27/1022 ,  H01L27/1052 ,  H01L27/1085 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/04 ,  H01L29/16 ,  H01L29/6609 ,  H01L29/66272 ,  H01L29/66666 ,  H01L29/732 ,  H01L29/868

Abstract: Some embodiments include methods of forming semiconductor constructions. A heavily-doped region is formed within a first semiconductor material, and a second semiconductor material is epitaxially grown over the first semiconductor material. The second semiconductor material is patterned to form circuit components, and the heavily-doped region is patterned to form spaced-apart buried lines electrically coupling pluralities of the circuit components to one another. At least some of the patterning of the heavily-doped region occurs simultaneously with at least some of the patterning of the second semiconductor material.

Abstract translation: 一些实施例包括形成半导体结构的方法。 在第一半导体材料内形成重掺杂区，并且在第一半导体材料上外延生长第二半导体材料。 将第二半导体材料图案化以形成电路部件，并且对重掺杂区域进行图案化以形成将多个电路部件彼此电耦合的间隔开的掩埋线。 至少一些重掺杂区域的图案化与第二半导体材料的至少一些图案化同时发生。

公开(公告)号：US20140017865A1

公开(公告)日：2014-01-16

申请号：US14030880

申请日：2013-09-18

Applicant: Micron Technology, Inc.

Inventor： Lars P Heineck ,  Shyam Surthi ,  Jaydip Guha

IPC: H01L29/66

CPC classification number: H01L27/10802 ,  H01L21/28132 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10891 ,  H01L29/66666 ,  H01L29/7788 ,  H01L29/7827 ,  H01L29/7841

Abstract: Some embodiments include memory arrays. The memory arrays may have digit lines under vertically-oriented transistors, with the digit lines interconnecting transistors along columns of the array. Each individual transistor may be directly over only a single digit line, with the single digit line being entirely composed of one or more metal-containing materials. The digit lines can be over a deck, and electrically insulative regions can be directly between the digit lines and the deck. Some embodiments include methods of forming memory arrays. A plurality of linear segments of silicon-containing material may be formed to extend upwardly from a base of the silicon-containing material. The base may be etched to form silicon-containing footings under the linear segments, and the footings may be converted into metal silicide. The linear segments may be patterned into a plurality of vertically-oriented transistor pedestals that extend upwardly from the metal silicide footings.

Abstract translation: 一些实施例包括存储器阵列。 存储器阵列可以在垂直取向的晶体管下面具有数字线，数字线将晶体管沿阵列的列互连。 每个单独的晶体管可以直接在单个数字线上，单个数字线完全由一个或多个含金属材料组成。 数字线可以在甲板上，电绝缘区域可以直接位于数字线和甲板之间。 一些实施例包括形成存储器阵列的方法。 可以形成多个含硅材料的线性段，以从含硅材料的基底向上延伸。 基底可以被蚀刻以在线性段下面形成含硅基底，并且基脚可以被转换成金属硅化物。 线性段可以被图案化成从金属硅化物基部向上延伸的多个垂直取向的晶体管基座。