公开(公告)号：US12279423B2

公开(公告)日：2025-04-15

申请号：US17654028

申请日：2022-03-08

Applicant: Micron Technology, Inc.

Inventor： Jun Fang ,  Fei Wang ,  Saniya Rathod ,  Rutuparna Narulkar ,  Matthew Park ,  Matthew J. King

IPC: H01L27/11521 ,  H01L21/768 ,  H01L27/11541 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11575 ,  H10B41/20 ,  H10B41/30 ,  H10B41/47 ,  H10B41/50 ,  H10B43/50

Abstract: A semiconductor device structure that comprises tiers of alternating dielectric levels and conductive levels and a carbon-doped silicon nitride over the tiers of the staircase structure. The carbon-doped silicon nitride excludes silicon carbon nitride. A method of forming the semiconductor device structure comprises forming stairs in a staircase structure comprising alternating dielectric levels and conductive levels. A carbon-doped silicon nitride is formed over the stairs, an oxide material is formed over the carbon-doped silicon nitride, and openings are formed in the oxide material. The openings extend to the carbon-doped silicon nitride. The carbon-doped silicon nitride is removed to extend the openings into the conductive levels of the staircase structure. Additional methods are disclosed.

公开(公告)号：US11177271B2

公开(公告)日：2021-11-16

申请号：US15705179

申请日：2017-09-14

Applicant: Micron Technology, Inc.

Inventor： Paolo Tessariol ,  Justin B. Dorhout ,  Indra V. Chary ,  Jun Fang ,  Matthew Park ,  Zhiqiang Xie ,  Scott D. Stull ,  Daniel Osterberg ,  Jason Reece ,  Jian Li

IPC: H01L27/11582 ,  H01L21/768 ,  H01L21/311 ,  H01L23/528 ,  H01L27/11556 ,  H01L21/02 ,  H01L29/10 ,  H01L23/522 ,  H01L27/11575 ,  H01L27/11565

Abstract: A device comprises an array of elevationally-extending transistors and a circuit structure adjacent and electrically coupled to the elevationally-extending transistors of the array. The circuit structure comprises a stair step structure comprising vertically-alternating tiers comprising conductive steps that are at least partially elevationally separated from one another by insulative material. Operative conductive vias individually extend elevationally through one of the conductive steps at least to a bottom of the vertically-alternating tiers and individually electrically couple to an electronic component below the vertically-alternating tiers. Dummy structures individually extend elevationally through one of the conductive steps at least to the bottom of the vertically-alternating tiers. Methods are also disclosed.

公开(公告)号：US12250812B2

公开(公告)日：2025-03-11

申请号：US18094906

申请日：2023-01-09

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Nancy M. Lomeli ,  John D. Hopkins ,  Jiewei Chen ,  Indra V. Chary ,  Jun Fang ,  Vladimir Samara ,  Kaiming Luo ,  Rita J. Klein ,  Xiao Li ,  Vinayak Shamanna

IPC: H01L21/306 ,  G11C5/02 ,  G11C5/06 ,  G11C16/04 ,  H10B41/27 ,  H10B43/27 ,  H10B43/30

Abstract: Some embodiments include an integrated assembly having a source structure, and having a stack of alternating conductive levels and insulative levels over the source structure. Cell-material-pillars pass through the stack. The cell-material-pillars are arranged within a configuration which includes a first memory-block-region and a second memory-block-region. The cell-material-pillars include channel material which is electrically coupled with the source structure. Memory cells are along the conductive levels and include regions of the cell-material-pillars. A panel is between the first and second memory-block-regions. The panel has a first material configured as a container shape. The container shape defines opposing sides and a bottom of a cavity. The panel has a second material within the cavity. The second material is compositionally different from the first material. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11889695B2

公开(公告)日：2024-01-30

申请号：US17504313

申请日：2021-10-18

Applicant: Micron Technology, Inc.

Inventor： Paolo Tessariol ,  Justin B. Dorhout ,  Indra V. Chary ,  Jun Fang ,  Matthew Park ,  Zhiqiang Xie ,  Scott D. Stull ,  Daniel Osterberg ,  Jason Reece ,  Jian Li

IPC: H01L27/11582 ,  H10B43/27 ,  H01L21/768 ,  H01L21/311 ,  H01L23/528 ,  H01L21/02 ,  H01L29/10 ,  H01L23/522 ,  H10B41/27 ,  H10B43/50 ,  H10B41/35 ,  H10B43/10

CPC classification number: H10B43/27 ,  H01L21/02636 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/528 ,  H01L23/5226 ,  H01L29/1037 ,  H10B41/27 ,  H10B41/35 ,  H10B43/50 ,  H10B43/10

Abstract: A device comprises an array of elevationally-extending transistors and a circuit structure adjacent and electrically coupled to the elevationally-extending transistors of the array. The circuit structure comprises a stair step structure comprising vertically-alternating tiers comprising conductive steps that are at least partially elevationally separated from one another by insulative material. Operative conductive vias individually extend elevationally through one of the conductive steps at least to a bottom of the vertically-alternating tiers and individually electrically couple to an electronic component below the vertically-alternating tiers. Dummy structures individually extend elevationally through one of the conductive steps at least to the bottom of the vertically-alternating tiers. Methods are also disclosed.

公开(公告)号：US11705385B2

公开(公告)日：2023-07-18

申请号：US17367990

申请日：2021-07-06

Applicant: Micron Technology, Inc.

Inventor： Indra V. Chary ,  Chet E. Carter ,  Anilkumar Chandolu ,  Justin B. Dorhout ,  Jun Fang ,  Matthew J. King ,  Brett D. Lowe ,  Matthew Park ,  Justin D. Shepherdson

IPC: H01L23/48 ,  H01L21/311 ,  H01L21/033 ,  H01L21/768 ,  H01L21/28 ,  H10B43/10 ,  H10B43/27 ,  H10B41/10 ,  H10B41/27

CPC classification number: H01L23/481 ,  H01L21/0337 ,  H01L21/31111 ,  H01L21/76897 ,  H01L29/40117 ,  H10B43/10 ,  H10B43/27 ,  H10B41/10 ,  H10B41/27

Abstract: A method used in forming a memory array and conductive through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. A mask is formed comprising horizontally-elongated trench openings and operative TAV openings above the stack. Etching is conducted of unmasked portions of the stack through the trench and operative TAV openings in the mask to form horizontally-elongated trench openings in the stack and to form operative TAV openings in the stack. Conductive material is formed in the operative TAV openings in the stack to form individual operative TAVs in individual of the operative TAV openings in the stack. A wordline-intervening structure is formed in individual of the trench openings in the stack.

公开(公告)号：US11069598B2

公开(公告)日：2021-07-20

申请号：US16444634

申请日：2019-06-18

Applicant: Micron Technology, Inc.

Inventor： Indra V. Chary ,  Chet E. Carter ,  Anilkumar Chandolu ,  Justin B. Dorhout ,  Jun Fang ,  Matthew J. King ,  Brett D. Lowe ,  Matthew Park ,  Justin D. Shepherdson

IPC: H01L23/48 ,  H01L27/11582 ,  H01L27/11565 ,  H01L21/311 ,  H01L21/033 ,  H01L21/768 ,  H01L21/28 ,  H01L27/11556 ,  H01L27/11519

Abstract: A method used in forming a memory array and conductive through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. A mask is formed comprising horizontally-elongated trench openings and operative TAV openings above the stack. Etching is conducted of unmasked portions of the stack through the trench and operative TAV openings in the mask to form horizontally-elongated trench openings in the stack and to form operative TAV openings in the stack. Conductive material is formed in the operative TAV openings in the stack to form individual operative TAVs in individual of the operative TAV openings in the stack. A wordline-intervening structure is formed in individual of the trench openings in the stack.

公开(公告)号：US20190081061A1

公开(公告)日：2019-03-14

申请号：US15705179

申请日：2017-09-14

Applicant: Micron Technology, Inc.

Inventor： Paolo Tessariol ,  Justin B. Dorhout ,  Indra V. Chary ,  Jun Fang ,  Matthew Park ,  Zhiqiang Xie ,  Scott D. Stull ,  Daniel Osterberg ,  Jason Reece ,  Jian Li

IPC: H01L27/11582 ,  H01L21/768 ,  H01L21/311 ,  H01L27/11556 ,  H01L21/02 ,  H01L29/10 ,  H01L23/522 ,  H01L23/528

Abstract: A device comprises an array of elevationally-extending transistors and a circuit structure adjacent and electrically coupled to the elevationally-extending transistors of the array. The circuit structure comprises a stair step structure comprising vertically-alternating tiers comprising conductive steps that are at least partially elevationally separated from one another by insulative material. Operative conductive vias individually extend elevationally through one of the conductive steps at least to a bottom of the vertically-alternating tiers and individually electrically couple to an electronic component below the vertically-alternating tiers. Dummy structures individually extend elevationally through one of the conductive steps at least to the bottom of the vertically-alternating tiers. Methods are also disclosed.

公开(公告)号：US20220189974A1

公开(公告)日：2022-06-16

申请号：US17654028

申请日：2022-03-08

Applicant: Micron Technology, Inc.

Inventor： Jun Fang ,  Fei Wang ,  Saniya Rathod ,  Rutuparna Narulkar ,  Matthew Park ,  Matthew J. King

IPC: H01L27/11521 ,  H01L27/11551 ,  H01L27/11541 ,  H01L21/768 ,  H01L27/11548 ,  H01L27/11575

Abstract: A semiconductor device structure that comprises tiers of alternating dielectric levels and conductive levels and a carbon-doped silicon nitride over the tiers of the staircase structure. The carbon-doped silicon nitride excludes silicon carbon nitride. A method of forming the semiconductor device structure comprises forming stairs in a staircase structure comprising alternating dielectric levels and conductive levels. A carbon-doped silicon nitride is formed over the stairs, an oxide material is formed over the carbon-doped silicon nitride, and openings are formed in the oxide material. The openings extend to the carbon-doped silicon nitride. The carbon-doped silicon nitride is removed to extend the openings into the conductive levels of the staircase structure. Additional methods are disclosed.

公开(公告)号：US20220037360A1

公开(公告)日：2022-02-03

申请号：US17504313

申请日：2021-10-18

Applicant: Micron Technology, Inc.

Inventor： Paolo Tessariol ,  Justin B. Dorhout ,  Indra V. Chary ,  Jun Fang ,  Matthew Park ,  Zhiqiang Xie ,  Scott D. Stull ,  Daniel Osterberg ,  Jason Reece ,  Jian Li

IPC: H01L27/11582 ,  H01L21/768 ,  H01L21/311 ,  H01L23/528 ,  H01L27/11556 ,  H01L21/02 ,  H01L29/10 ,  H01L23/522 ,  H01L27/11575

Abstract: A device comprises an array of elevationally-extending transistors and a circuit structure adjacent and electrically coupled to the elevationally-extending transistors of the array. The circuit structure comprises a stair step structure comprising vertically-alternating tiers comprising conductive steps that are at least partially elevationally separated from one another by insulative material. Operative conductive vias individually extend elevationally through one of the conductive steps at least to a bottom of the vertically-alternating tiers and individually electrically couple to an electronic component below the vertically-alternating tiers. Dummy structures individually extend elevationally through one of the conductive steps at least to the bottom of the vertically-alternating tiers. Methods are also disclosed.

公开(公告)号：US20190067306A1

公开(公告)日：2019-02-28

申请号：US15685690

申请日：2017-08-24

Applicant: Micron Technology, Inc.

Inventor： Jun Fang ,  Fei Wang ,  Saniya Rathod ,  Rutuparna Narulkar ,  Matthew Park ,  Matthew J. King

IPC: H01L27/11521 ,  H01L27/11551 ,  H01L27/11541

Abstract: A semiconductor device structure that comprises tiers of alternating dielectric levels and conductive levels and a carbon-doped silicon nitride over the tiers of the staircase structure. The carbon-doped silicon nitride excludes silicon carbon nitride. A method of forming the semiconductor device structure comprises forming stairs in a staircase structure comprising alternating dielectric levels and conductive levels. A carbon-doped silicon nitride is formed over the stairs, an oxide material is formed over the carbon-doped silicon nitride, and openings are formed in the oxide material. The openings extend to the carbon-doped silicon nitride. The carbon-doped silicon nitride is removed to extend the openings into the conductive levels of the staircase structure. Additional methods are disclosed.