公开(公告)号：US20140302674A1

公开(公告)日：2014-10-09

申请号：US14311405

申请日：2014-06-23

Applicant: QUALCOMM Incorporated

Inventor： Vidhya RAMACHANDRAN ,  Shiqun GU

IPC: H01L21/768

CPC classification number: H01L21/76898 ,  H01L21/7682 ,  H01L21/76831 ,  H01L23/481 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor die including strain relief for through substrate vias (TSVs). A method for strain relief of TSVs includes defining a through substrate via cavity in a substrate. The method also includes depositing an isolation layer in the cavity. The method further includes filling the cavity with a conductive material. The method also includes removing a portion of the isolation layer to create a recessed portion.

Abstract translation: 包括通过衬底通孔（TSV）的应变消除的半导体管芯。 用于TSV应变消除的方法包括在衬底中限定通孔的通孔。 该方法还包括在空腔中沉积隔离层。 该方法还包括用导电材料填充空腔。 该方法还包括去除隔离层的一部分以形成凹陷部分。

公开(公告)号：US20160013136A1

公开(公告)日：2016-01-14

申请号：US14329883

申请日：2014-07-11

Applicant: QUALCOMM Incorporated

Inventor： Vidhya RAMACHANDRAN ,  Zhongping BAO

IPC: H01L23/00 ,  H01L25/00 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L23/562 ,  H01L24/16 ,  H01L24/32 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/37001 ,  H01L2924/00

Abstract: Methods and apparatuses, wherein the method includes reducing stacking stress. The method couples a first die to a compliant layer. The method couples a second die to the compliant layer, wherein the compliant layer at least partially covers a portion of an interface between the first die and the second die, and wherein the compliant layer is formed in a trench in the second die.

Abstract translation: 方法和装置，其中所述方法包括降低堆垛应力。 该方法将第一管芯耦合到柔性层。 该方法将第二管芯耦合到柔性层，其中柔顺层至少部分地覆盖第一管芯和第二管芯之间的界面的一部分，并且其中柔顺层形成在第二管芯中的沟槽中。

公开(公告)号：US20150250058A1

公开(公告)日：2015-09-03

申请号：US14463367

申请日：2014-08-19

Applicant: QUALCOMM Incorporated

Inventor： Vidhya RAMACHANDRAN ,  Urmi RAY ,  Ravindra Vaman SHENOY ,  Kwan-Yu LAI ,  Jon Bradley LASITER

IPC: H05K1/18 ,  H01L21/768 ,  H01L21/28 ,  H01L23/538

CPC classification number: H05K1/185 ,  H01L21/28008 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/84 ,  H01L23/147 ,  H01L23/49827 ,  H01L23/5384 ,  H01L25/065 ,  H01L27/0629 ,  H01L27/0688 ,  H01L27/12 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/00

Abstract: An integrated interposer between a first component and a second component includes a substrate. The substrate may have thermal and/or mechanical properties with values lying between the thermal and/or mechanical properties of the first component and the second component. Active devices are disposed on a first surface of the substrate. A contact layer is coupled to the active devices and configured to couple at least the first component and a third component to the integrated interposer. At least one through via(s) is coupled to the contact layer and extends through the substrate to a second surface of the substrate. An interconnect layer is disposed on the second surface of the substrate and coupled to the at least one through via(s). The interconnect layer is configured to couple the second component to the integrated interposer.

Abstract translation: 第一部件和第二部件之间的集成插入件包括基板。 衬底可以具有热和/或机械性能，其中值位于第一部件和第二部件的热和/或机械性能之间。 有源器件设置在衬底的第一表面上。 接触层耦合到有源器件并且被配置为将至少第一部件和第三部件耦合到集成插入器。 至少一个通孔连接到接触层并且延伸穿过衬底到衬底的第二表面。 互连层设置在衬底的第二表面上并且耦合到至少一个通孔。 互连层被配置为将第二组件耦合到集成插入器。

公开(公告)号：US20160126291A1

公开(公告)日：2016-05-05

申请号：US14527267

申请日：2014-10-29

Applicant: QUALCOMM Incorporated

Inventor： Yu LU ,  Vidhya RAMACHANDRAN ,  Seung Hyuk KANG

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2463 ,  H01L21/485 ,  H01L23/49827 ,  H01L23/538 ,  H01L23/5382 ,  H01L23/5383 ,  H01L25/0655 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/16 ,  H01L2224/16227 ,  H01L2924/15192 ,  H01L2924/15311

Abstract: An integrated interposer may include a substrate and a resistive-type non-volatile memory (NVM) array(s). The integrated interposer may also include a contact layer on a first surface of the substrate. The contact layer may include interconnections configured to couple the resistive-type NVM array(s) to a die(s). The resistive-type NVM array(s) may be partially embedded within the contact layer of the integrated interposer.

Abstract translation: 集成插入器可以包括衬底和电阻型非易失性存储器（NVM）阵列。 集成插入件还可以包括在衬底的第一表面上的接触层。 接触层可以包括配置成将电阻型NVM阵列耦合到管芯的互连。 电阻型NVM阵列可以部分地嵌入在集成插入器的接触层内。

公开(公告)号：US20160095221A1

公开(公告)日：2016-03-31

申请号：US14499151

申请日：2014-09-27

Applicant: QUALCOMM Incorporated

Inventor： Vidhya RAMACHANDRAN ,  Urmi RAY

IPC: H05K1/18 ,  H05K3/30 ,  H05K3/40 ,  H05K1/11

CPC classification number: H05K1/181 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/60 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0657 ,  H01L27/0629 ,  H01L27/0694 ,  H01L27/1218 ,  H01L28/40 ,  H01L29/945 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05568 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06568 ,  H01L2924/10253 ,  H01L2924/1203 ,  H01L2924/1304 ,  H01L2924/14 ,  H01L2924/15311 ,  H05K1/115 ,  H05K3/301 ,  H05K3/303 ,  H05K3/4038 ,  H05K2201/10166 ,  H05K2201/10174 ,  H05K2201/10515 ,  H01L2924/014 ,  H01L2924/00

Abstract: Systems and methods include a first semiconductor die with a substrate having a first side and a second side opposite to the first side. A first set of electronic elements is integrated on the first side. A second set of electronic elements is integrated on the second side. One or more through-substrate vias through the substrate are used to couple one or more of the first set of electronic elements and one or more of the second set of electronic elements. The through-substrate vias may be through-silicon vias (TSVs) or a through-glass vias (TGVs). The first semiconductor die may be stacked with a second semiconductor die, with the first side or the second side of the first semiconductor die interfacing an active side of the second semiconductor die.

Abstract translation: 系统和方法包括具有第一侧和与第一侧相对的第二侧的基板的第一半导体管芯。 第一组电子元件集成在第一面上。 第二组电子元件集成在第二侧。 通过衬底的一个或多个贯穿衬底通孔用于耦合第一组电子元件中的一个或多个以及第二组电子元件中的一个或多个。 贯通衬底通孔可以是硅通孔（TSV）或透玻璃通孔（TGV）。 第一半导体管芯可以与第二半导体管芯堆叠，第一半导体管芯的第一侧或第二侧与第二半导体管芯的有源侧相接。

公开(公告)号：US20160043068A1

公开(公告)日：2016-02-11

申请号：US14454851

申请日：2014-08-08

Applicant: QUALCOMM Incorporated

Inventor： Vidhya RAMACHANDRAN ,  Shiqun GU

IPC: H01L27/02 ,  H01L21/48 ,  H01L23/498 ,  H01L49/02

CPC classification number: H01L27/0288 ,  H01L21/486 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/5223 ,  H01L23/642 ,  H01L25/0652 ,  H01L25/16 ,  H01L27/0255 ,  H01L28/90 ,  H01L2224/16227 ,  H01L2924/15311

Abstract: An integrated interposer includes an interposer substrate including at least a first portion of a 3D passive device within an active region of the interposer substrate. The integrated interposer also includes an inter-conductive dielectric layer on an active surface of the active region of the interposer substrate, the inter-conductive dielectric layer including at least a second portion of the 3D passive device. The integrated interposer further includes a contact layer coupled to the 3D passive devices and configured to couple at least one die to the integrated interposer. The integrated interposer also includes at least one through via coupled to the contact layer and extending through the interposer substrate to a passive surface of the interposer substrate. The integrated interposer further includes an interconnect layer on the passive surface of the interposer substrate and coupled to the at least one through via.

Abstract translation: 集成插入器包括插入器基板，其包括在内插器基板的有源区域内的3D无源器件的至少第一部分。 该集成插入器还包括在该插入器基板的有源区域的有源表面上的导电介电层，该导电介质层至少包括该3D无源器件的第二部分。 集成中介层还包括耦合到3D无源器件并被配置为将至少一个管芯耦合到集成插入器的接触层。 集成插入器还包括至少一个通孔，其连接到接触层并且延伸穿过插入器衬底到内插器衬底的无源表面。 集成插入器还包括在插入器基板的被动表面上并且耦合到至少一个通孔的互连层。