公开(公告)号：US20230378072A1

公开(公告)日：2023-11-23

申请号：US17857887

申请日：2022-07-05

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Shuai-Lin Liu ,  Nai-Hao Kao ,  Chao-Chiang Pu ,  Yi-Min Fu ,  Yu-Po Wang

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/5381 ,  H01L25/0655 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/49816 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/565 ,  H01L23/49838 ,  H01L23/49822 ,  H01L21/4857 ,  H01L24/16

Abstract: An electronic package is provided, in which a plurality of electronic elements are disposed on a plurality of carrier structures, and at least one bridging element is disposed between at least two of the carrier structures to electrically bridge the two carrier structures. Therefore, when there is a need to increase the function of the electronic package, only one electronic element is arranged on a single carrier structure, and there is no need to increase the panel area of the carrier structure, so as to facilitate the control of the panel area of the carrier structure and avoid warpage of the carrier structure due to the oversized panel.

公开(公告)号：US20220399246A1

公开(公告)日：2022-12-15

申请号：US17829533

申请日：2022-06-01

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Yi-Min Fu ,  Chi-Ching Ho ,  Yu-Po Wang

IPC: H01L23/373 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56

Abstract: An electronic package is provided, where a laterally diffused metal oxide semiconductor (LDMOS) type electronic structure is mounted onto a complementary metal oxide semiconductor (CMOS) type electronic element to be integrated into a chip module, thereby shortening electrical transmission path between the electronic structure and the electronic element so as to reduce the communication time between the electronic structure and the electronic element.

公开(公告)号：US12051641B2

公开(公告)日：2024-07-30

申请号：US17527434

申请日：2021-11-16

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Yi-Min Fu ,  Chi-Ching Ho ,  Cheng-Yu Kang ,  Yu-Po Wang

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/367 ,  H01L23/00

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/367 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/73 ,  H01L2224/73204 ,  H01L2924/3511

Abstract: Provided is an electronic package providing a circuit structure having auxiliary circuit layers. Further, an electronic component is disposed on the circuit structure and electrically connected to the auxiliary circuit layers. In addition, an encapsulant covers the electronic component, and the circuit structure is disposed on the package substrate having a plurality of main circuit layers, such that the main circuit layers are electrically connected to the auxiliary circuit layers. As such, a number of layers of the auxiliary circuit layers is used to replace a layer number configuration of the main circuit layers.

公开(公告)号：US20230282586A1

公开(公告)日：2023-09-07

申请号：US17740796

申请日：2022-05-10

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Chao-Chiang Pu ,  Chi-Ching Ho ,  Yi-Min Fu ,  Yu-Po Wang ,  Shuai-Lin Liu

IPC: H01L23/538 ,  H01L25/10 ,  H01L23/48 ,  H01L25/00

CPC classification number: H01L23/5381 ,  H01L25/105 ,  H01L23/481 ,  H01L25/50 ,  H01L23/5386 ,  H01L24/16

Abstract: An electronic package is provided in which a chip packaging module, an electronic element having a plurality of contacts, and an electronic connector are disposed on a routing structure of a carrier component, so as to communicatively connect with the chip packaging module via the electronic element and the electronic connector, thereby increasing a signal transmission speed.

公开(公告)号：US12199047B2

公开(公告)日：2025-01-14

申请号：US17572001

申请日：2022-01-10

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Chao-Chiang Pu ,  Chi-Ching Ho ,  Yi-Min Fu ,  Yu-Po Wang ,  Po-Yuan Su

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L23/58 ,  H01L23/42 ,  H05K1/02

Abstract: An electronic package is provided in which an electronic module and a heat dissipation structure combined with the electronic module are disposed on a carrier structure, and at least one adjustment structure is coupled with the heat dissipation structure and located around the electronic module. Therefore, the adjustment structure disperses thermal stress to avoid warpage of the electronic module.

公开(公告)号：US20240038685A1

公开(公告)日：2024-02-01

申请号：US17950914

申请日：2022-09-22

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Chao-Chiang Pu ,  Chi-Ching Ho ,  Yi-Min Fu ,  Yu-Po Wang ,  Fang-Lin Tsai

IPC: H01L23/00 ,  H01L25/10 ,  H01L23/498 ,  H01L23/538 ,  H01L21/48

CPC classification number: H01L23/562 ,  H01L24/16 ,  H01L24/73 ,  H01L24/32 ,  H01L25/105 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5381 ,  H01L23/5385 ,  H01L23/5386 ,  H01L21/4817 ,  H01L2924/37001 ,  H01L2924/3511 ,  H01L2224/73204 ,  H01L2224/32225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/16235

Abstract: An electronic package is provided and includes an electronic structure and a plurality of conductive pillars embedded in a cladding layer, a circuit structure formed on the cladding layer, and a reinforcing member bonded to a side surface of the cladding layer, where a plurality of electronic elements are disposed on and electrically connected to the circuit structure, such that the electronic structure electrically bridges any two of the electronic elements via the circuit structure, so as to enhance the structural strength of the electronic package and avoid warpage by means of the design of the reinforcing member.

公开(公告)号：US09356008B2

公开(公告)日：2016-05-31

申请号：US14616013

申请日：2015-02-06

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Cheng-Chia Chiang ,  Hsin-Ta Lin ,  Fu-Tang Huang ,  Yu-Po Wang ,  Lung-Yuan Wang ,  Chu-Chi Hsu ,  Chia-Kai Shih

IPC: H01L25/16 ,  H01L25/00 ,  H01L23/00 ,  H01L23/42 ,  H01L23/31

CPC classification number: H01L25/162 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/42 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/562 ,  H01L23/564 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05015 ,  H01L2224/05016 ,  H01L2224/05078 ,  H01L2224/0519 ,  H01L2224/05561 ,  H01L2224/05582 ,  H01L2224/056 ,  H01L2224/05611 ,  H01L2224/06132 ,  H01L2224/06181 ,  H01L2224/11825 ,  H01L2224/12105 ,  H01L2224/13014 ,  H01L2224/13017 ,  H01L2224/13023 ,  H01L2224/13078 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1319 ,  H01L2224/13582 ,  H01L2224/13671 ,  H01L2224/1369 ,  H01L2224/1401 ,  H01L2224/141 ,  H01L2224/16145 ,  H01L2224/16147 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/17181 ,  H01L2224/17517 ,  H01L2224/17519 ,  H01L2224/291 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83101 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2225/06513 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2924/0635 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/18161 ,  H01L2924/381 ,  H01L2924/3841 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01082 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/07025 ,  H01L2924/00

Abstract: A semiconductor package is provided, which includes: a first semiconductor device having a first top surface and a first bottom surface opposite to the first top surface; a plurality of conductive balls formed on the first top surface of the first semiconductor device; a second semiconductor device having a second top surface and a second bottom surface opposite to the second top surface; and a plurality of conductive posts formed on the second bottom surface of the second semiconductor device and correspondingly bonded to the conductive balls for electrically connecting the first semiconductor device and the second semiconductor device, wherein the conductive posts have a height less than 300 um. Therefore, the present invention can easily control the height of the semiconductor package and is applicable to semiconductor packages having fine-pitch conductive balls.

Abstract translation: 提供一种半导体封装，其包括：第一半导体器件，其具有第一顶表面和与第一顶表面相对的第一底表面; 形成在所述第一半导体器件的所述第一顶表面上的多个导电球; 具有第二顶表面和与第二顶表面相对的第二底表面的第二半导体器件; 以及形成在所述第二半导体器件的所述第二底表面上并相应地接合到所述导电球以用于电连接所述第一半导体器件和所述第二半导体器件的多个导电柱，其中所述导电柱的高度小于300μm。 因此，本发明可以容易地控制半导体封装的高度，并且可应用于具有细间距导电球的半导体封装。

公开(公告)号：US09269677B2

公开(公告)日：2016-02-23

申请号：US14531226

申请日：2014-11-03

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chia-Yin Chen ,  Yu-Ching Liu ,  Yueh-Chiung Chang ,  Yu-Po Wang

IPC: H01L23/00

CPC classification number: H01L24/03 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/03462 ,  H01L2224/03552 ,  H01L2224/0381 ,  H01L2224/03831 ,  H01L2224/04042 ,  H01L2224/27013 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2224/8385 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A packaging substrate and a semiconductor package using the packaging substrate are provided. The packaging substrate includes: a substrate body having a die attach area, a circuit layer formed around the die attach area and having a plurality of conductive traces each having a wire bonding pad, and a surface treatment layer formed on the wire bonding pads. Therein, only one of the conductive traces is connected to an electroplating line so as to prevent cross-talk that otherwise occurs between conductive traces due to too many electroplating lines in the prior art.

Abstract translation: 提供了使用封装基板的封装基板和半导体封装。 封装基板包括：具有管芯附着区域的基板主体，形成在管芯附着区域周围的电路层，并且具有多个导线，每个导线具有引线焊盘，以及形成在引线接合焊盘上的表面处理层。 其中，仅有一个导电迹线连接到电镀线，以便防止由于现有技术中的电镀线太多导致的导电迹线之间的串扰。

公开(公告)号：US12176291B2

公开(公告)日：2024-12-24

申请号：US17740796

申请日：2022-05-10

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Chao-Chiang Pu ,  Chi-Ching Ho ,  Yi-Min Fu ,  Yu-Po Wang ,  Shuai-Lin Liu

IPC: H01L21/00 ,  H01L23/48 ,  H01L23/538 ,  H01L25/00 ,  H01L25/10 ,  H01L23/00

Abstract: An electronic package is provided in which a chip packaging module, an electronic element having a plurality of contacts, and an electronic connector are disposed on a routing structure of a carrier component, so as to communicatively connect with the chip packaging module via the electronic element and the electronic connector, thereby increasing a signal transmission speed.

公开(公告)号：US20230253331A1

公开(公告)日：2023-08-10

申请号：US17897523

申请日：2022-08-29

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Yi-Min Fu ,  Chi-Ching Ho ,  Chao-Chiang Pu ,  Yu-Po Wang

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/5381 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/105 ,  H01L23/5385 ,  H01L23/5386 ,  H01L21/565 ,  H01L21/563 ,  H01L23/3135 ,  H01L23/3128 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/182 ,  H01L2924/3511 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/107

Abstract: An electronic package is provided, in which an electronic module and at least one support member are disposed on a substrate structure having a circuit layer, such that the stress on the substrate structure is dispersed through the at least one support member to eliminate the problem of stress concentration and prevent the substrate structure from warping.