公开(公告)号：US20180040514A1

公开(公告)日：2018-02-08

申请号：US15784764

申请日：2017-10-16

Applicant: STMicroelectronics Pte Ltd

Inventor： Kim-Yong Goh ,  Xueren Zhang ,  Yiyi Ma

IPC: H01L21/78

CPC classification number: H01L21/78 ,  B81B7/0048 ,  H01L23/053 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L27/14618 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/27013 ,  H01L2224/29101 ,  H01L2224/29198 ,  H01L2224/32058 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/83007 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/10157 ,  H01L2924/10158 ,  H01L2924/12042 ,  H01L2924/16151 ,  H01L2924/014

Abstract: Embodiments are directed to a package that includes an electric device having a recess. In one embodiment, the electric device is a sensor and the recess reduces signal drift of the sensor caused by thermal expansion of the package. In another embodiment, the recess is substantially filled with adhesive material, thus increasing adhesion between the electric device and a substrate of the package while at the same time allowing for lower adhesive fillets.

公开(公告)号：US09576912B1

公开(公告)日：2017-02-21

申请号：US14957865

申请日：2015-12-03

Applicant: STMICROELECTRONICS PTE LTD

Inventor： Yiyi Ma ,  Kim-Yong Goh ,  Xueren Zhang

IPC: H01L23/12 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/3192 ,  H01L24/02 ,  H01L24/05 ,  H01L24/13 ,  H01L24/94 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0391 ,  H01L2224/05008 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/94 ,  H01L2924/014 ,  H01L2924/01029 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2924/01047 ,  H01L2224/023 ,  H01L2924/07025

Abstract: A wafer level chip scale package (WLCSP) includes a semiconductor substrate, a back end of line (BEOL) layer on the semiconductor substrate and having a peripheral edge recessed inwardly from an adjacent peripheral edge of the semiconductor substrate. A first dielectric layer is over the BEOL layer and wraps around the peripheral edge of the BEOL layer. A redistribution layer is over the first dielectric layer and a second dielectric layer is over the redistribution layer.

Abstract translation: 晶片级芯片级封装（WLCSP）包括半导体衬底，半导体衬底上的后端（BEOL）层，并且具有从半导体衬底的相邻外围边缘向内凹陷的外围边缘。 第一电介质层在BEOL层上方并且缠绕在BEOL层的外围边缘周围。 再分布层在第一介电层上方，第二介电层位于再分布层上。

公开(公告)号：US09379034B1

公开(公告)日：2016-06-28

申请号：US14585566

申请日：2014-12-30

Applicant: STMICROELECTRONICS PTE LTD

Inventor： Kim-Yong Goh ,  Yiyi Ma ,  Xueren Zhang

IPC: H01L23/10 ,  H01L23/31 ,  H01L23/498 ,  H01L23/367 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L23/3135 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/49816 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of making an electronic device may include positioning an integrated circuit (IC) die on an upper surface of a grid array substrate having connections on a lower surface thereof and coupling respective bond pads of the IC die to the grid array with bond wires. The method may also include forming a first encapsulating layer over the IC die and bond wires and positioning a heat spreader on the substrate above the first encapsulating layer after forming the first encapsulating layer. The method may further include forming a second encapsulating layer over the first encapsulating layer and embedding the heat spreader in the second encapsulating layer.

Abstract translation: 制造电子设备的方法可以包括将集成电路（IC）管芯定位在具有在其下表面上的连接的栅格阵列衬底的上表面上，并且将IC芯片的各个接合焊盘与接合线耦合到栅极阵列。 该方法还可以包括在IC芯片上方形成第一封装层，并且在形成第一封装层之后，将第一封装层上的基板上的散热器定位在第一封装层上方的基板上。 该方法还可以包括在第一封装层上形成第二封装层，并将散热器嵌入第二封装层中。

公开(公告)号：US09620438B2

公开(公告)日：2017-04-11

申请号：US14615673

申请日：2015-02-06

Applicant: STMicroelectronics (Malta) Ltd ,  STMicroelectronics S.r.l. ,  STMicroelectronics Pte Ltd

Inventor： Roseanne Duca ,  Valter Motta ,  Xueren Zhang ,  Kim-Yong Goh

IPC: H01L23/02 ,  H01L23/495

CPC classification number: H01L23/49568 ,  H01L23/4334 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2924/18301 ,  H01L2924/00014

Abstract: An electronic device includes an integrated circuit chip mounted to a heat slug. The heat slug has a peripheral region having first thickness along a first direction, the peripheral region surrounding a recess region (having a second, smaller, thickness along the first direction) that defines a chip mounting surface along a second direction perpendicular to the first direction. The recess region defines side borders and a nook extends into the heat slug along the side borders. An insulating body embeds the integrated circuit one chip and heat slug. Material of the insulating body fills the nook.

公开(公告)号：US20140291782A1

公开(公告)日：2014-10-02

申请号：US13853645

申请日：2013-03-29

Applicant: STMICROELECTRONICS PTE LTD.

Inventor： Kim-Yong Goh ,  Yiyi Ma ,  Wei Zhen Goh

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81B7/0058 ,  B81C2203/0109 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/16151 ,  H01L2924/16152 ,  H01L2924/00014

Abstract: Methods and devices for packaging integrated circuits. A packaged device may include an integrated circuit, a first packaging component including a patterned surface, and a second packaging component. The patterned surface of the first packaging component may be adhesively coupled to a surface of the second packaging component or a surface of the integrated circuit. The integrated circuit may be at least partially enclosed between the first and second packaging components. A packaging method may include patterning a surface of a packaging component of an integrated circuit package. The surface of the packaging component may be for adhesively coupling to a second component to at least partially enclose an integrated circuit in the integrated circuit package.

Abstract translation: 集成电路封装的方法和装置。 封装的装置可以包括集成电路，包括图案化表面的第一包装部件和第二包装部件。 第一包装部件的图案化表面可以粘合地耦合到第二包装部件的表面或集成电路的表面。 集成电路可以至少部分地封装在第一和第二封装部件之间。 包装方法可以包括图案化集成电路封装的封装部件的表面。 包装部件的表面可以用于粘合地耦合到第二部件以至少部分地封装集成电路封装中的集成电路。

公开(公告)号：US09824924B2

公开(公告)日：2017-11-21

申请号：US13853856

申请日：2013-03-29

Applicant: STMicroelectronics Pte Ltd.

Inventor： Kim-Yong Goh ,  Xueren Zhang ,  Yiyi Ma

IPC: H01L23/02 ,  H01L21/78 ,  H01L23/00 ,  B81B7/00 ,  H01L23/053

CPC classification number: H01L21/78 ,  B81B7/0048 ,  H01L23/053 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/27013 ,  H01L2224/29101 ,  H01L2224/29198 ,  H01L2224/32058 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/83007 ,  H01L2924/00014 ,  H01L2924/10157 ,  H01L2924/10158 ,  H01L2924/12042 ,  H01L2924/16151 ,  H01L2924/014 ,  H01L2924/00

Abstract: Embodiments are directed to a package that includes an electric device having a recess. In one embodiment, the electric device is a sensor and the recess reduces signal drift of the sensor caused by thermal expansion of the package. In another embodiment, the recess is substantially filled with adhesive material, thus increasing adhesion between the electric device and a substrate of the package while at the same time allowing for lower adhesive fillets.

公开(公告)号：US09257372B2

公开(公告)日：2016-02-09

申请号：US14032075

申请日：2013-09-19

Applicant: STMicroelectronics (Malta) Ltd ,  STMicroelectronics Pte Ltd

Inventor： Roseanne Duca ,  Kim-Yong Goh ,  Xueren Zhang ,  Kevin Formosa

IPC: H01L23/495 ,  H01L21/56 ,  G01P1/02 ,  H01L23/31 ,  H05K3/30 ,  H05K3/34

CPC classification number: H01L23/49541 ,  G01P1/023 ,  H01L21/56 ,  H01L21/565 ,  H01L23/3107 ,  H01L2224/45147 ,  H01L2224/48247 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/1461 ,  H01L2924/1815 ,  H05K3/303 ,  H05K3/3421 ,  H05K2201/09781 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/01005 ,  H01L2224/45099

Abstract: A surface mount package of a semiconductor device, has: an encapsulation, housing at least one die including semiconductor material; and electrical contact leads, protruding from the encapsulation to be electrically coupled to contact pads of a circuit board; the encapsulation has a main face designed to face a top surface of the circuit board, which is provided with coupling features designed for mechanical coupling to the circuit board to increase a resonant frequency of the mounted package. The coupling features envisage at least a first coupling recess defined within the encapsulation starting from the main face, designed to be engaged by a corresponding coupling element fixed to the circuit board, thereby restricting movements of the mounted package.

Abstract translation: 半导体器件的表面贴装封装具有：封装，容纳至少一个包含半导体材料的管芯; 以及电接触引线，从封装凸出以电耦合到电路板的接触焊盘; 封装具有设计成面向电路板的顶表面的主面，该主面具有设计成用于机械耦合到电路板的耦合特征，以增加安装封装的谐振频率。 耦合特征设想至少一个第一耦合凹槽，其限定在从主面开始的封装内，被设计成由固定到电路板的对应耦合元件接合，从而限制安装的封装的移动。

公开(公告)号：US08822267B2

公开(公告)日：2014-09-02

申请号：US13655036

申请日：2012-10-18

Applicant: STMicroelectronics Pte Ltd.

Inventor： How Yuan Hwang ,  Jay Maghirang ,  Yaohuang Huang ,  Kim-Yong Goh ,  Phone Maw Hla ,  Edmond Soon

IPC: H01L21/00

CPC classification number: H01L21/561 ,  H01L21/568 ,  H01L24/11 ,  H01L24/13 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L24/92 ,  H01L24/96 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16265 ,  H01L2224/17181 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/8121 ,  H01L2224/8123 ,  H01L2224/81815 ,  H01L2224/9211 ,  H01L2224/96 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2224/19 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are related to manufacturing system-in-packages at wafer-level. In particular, various embodiments are directed to adhering a first wafer to a second wafer and adhering solder balls to contact pads of the first wafer. In one embodiment, a first wafer having first and second surfaces is provided. The first wafer includes bond pads located on the first surface that are coupled to a respective semiconductor device located in the first wafer. A second wafer having an electrical component located therein is provided. A conductive adhesive is provided on at least one of the first wafer and the second wafer. Conductive balls are provided on the bond pads on the first surface of the first wafer. The conductive balls and the conductive adhesive are heated to cause the conductive balls to adhere to the bond pad and the conductive adhesive to adhere the first wafer to the second wafer.

Abstract translation: 本公开的实施例涉及在晶片级制造系统级封装。 具体地，各种实施例涉及将第一晶片粘附到第二晶片并将焊球粘附到第一晶片的接触焊盘。 在一个实施例中，提供具有第一和第二表面的第一晶片。 第一晶片包括位于第一表面上的接合焊盘，其耦合到位于第一晶片中的相应半导体器件。 提供了具有位于其中的电气部件的第二晶片。 在第一晶片和第二晶片中的至少一个上提供导电粘合剂。 导电球设置在第一晶片的第一表面上的接合焊盘上。 导电球和导电粘合剂被加热以使导电球粘附到接合焊盘和导电粘合剂以将第一晶片粘附到第二晶片。

公开(公告)号：US09679870B2

公开(公告)日：2017-06-13

申请号：US14565484

申请日：2014-12-10

Applicant: STMICROELECTRONICS PTE LTD

Inventor： Yiyi Ma ,  Kim-Yong Goh ,  Xueren Zhang ,  Wei Zhen Goh

IPC: H01L23/00 ,  H01L23/482 ,  H01L23/495 ,  H01L23/31

CPC classification number: H01L24/85 ,  H01L23/3107 ,  H01L23/4822 ,  H01L23/49555 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48177 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An integrated circuit (IC) device includes an IC and encapsulating material surrounding the IC. Leads are coupled to the IC and extend outwardly from sides of the encapsulating material, with each lead having three contiguous exposed segments with upper and lower bends defining a Z-shape. In another example, the leads include an upper horizontal segment, lower horizontal segment, and intermediate curved segment extending upwardly from the upper horizontal segment and downwardly to the lower horizontal segment.

公开(公告)号：US08907465B2

公开(公告)日：2014-12-09

申请号：US13853645

申请日：2013-03-29

Applicant: STMicroelectronics Pte Ltd.

Inventor： Kim-Yong Goh ,  Yiyi Ma ,  Wei Zhen Goh

IPC: H01L23/02 ,  B81C1/00 ,  B81B7/00

CPC classification number: B81B7/0058 ,  B81C2203/0109 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/16151 ,  H01L2924/16152 ,  H01L2924/00014

Abstract: Methods and devices for packaging integrated circuits. A packaged device may include an integrated circuit, a first packaging component including a patterned surface, and a second packaging component. The patterned surface of the first packaging component may be adhesively coupled to a surface of the second packaging component or a surface of the integrated circuit. The integrated circuit may be at least partially enclosed between the first and second packaging components. A packaging method may include patterning a surface of a packaging component of an integrated circuit package. The surface of the packaging component may be for adhesively coupling to a second component to at least partially enclose an integrated circuit in the integrated circuit package.

Abstract translation: 集成电路封装的方法和装置。 封装的装置可以包括集成电路，包括图案化表面的第一包装部件和第二包装部件。 第一包装部件的图案化表面可以粘合地耦合到第二包装部件的表面或集成电路的表面。 集成电路可以至少部分地封装在第一和第二封装部件之间。 包装方法可以包括图案化集成电路封装的封装部件的表面。 包装部件的表面可以用于粘合地耦合到第二部件以至少部分地封装集成电路封装中的集成电路。