公开(公告)号：US20250006606A1

公开(公告)日：2025-01-02

申请号：US18416008

申请日：2024-01-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYUNJU LEE ,  GYUHO KANG ,  SUNG KEUN PARK ,  KWANGOK JEONG ,  JAEMOK JUNG ,  JU-IL CHOI

IPC: H01L23/498 ,  H01L23/00

Abstract: A semiconductor package may include: a substrate; a seed layer on a first surface of the substrate; a pad on the seed layer and including a first metal layer and a second metal layer on the first metal layer; an insulating layer on the first surface and including a side surface in contact with the second metal layer; and a semiconductor chip above a second surface of the substrate. An interface between the side surface of the insulating layer and the second metal layer may be nonplanar.

公开(公告)号：US20170358545A1

公开(公告)日：2017-12-14

申请号：US15440621

申请日：2017-02-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JU-IL CHOI ,  HYOJU KIM ,  KWANGJIN MOON ,  SUJEONG PARK ,  JUBIN SEO ,  NAEIN LEE ,  HO-JIN LEE

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0345 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05564 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11614 ,  H01L2224/11849 ,  H01L2224/13007 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13026 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16146 ,  H01L2224/16237 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A pad is disposed on a substrate. A bump structure is disposed on the pad and electrically connected to the pad. The bump structure includes a first copper layer and a second copper layer sequentially stacked on the pad and a solder ball on the second copper layer. A first X-ray diffraction (XRD) peak intensity ratio of (111) plane to (200) plane of the first copper layer is greater than a second XRD peak intensity ratio of (111) plane to (200) plane of the second copper layer.

公开(公告)号：US20240429176A1

公开(公告)日：2024-12-26

申请号：US18417494

申请日：2024-01-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： JU-IL CHOI ,  KWANGOK JEONG ,  JAEMOK JUNG ,  JEONGGI JIN ,  TAE OH HA ,  HONGSEO HEO

IPC: H01L23/544 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538

Abstract: A semiconductor package including: a first redistribution structure; a semiconductor chip on the first redistribution structure; a pad insulation layer on a lower surface of the first redistribution structure; a conductive pad extending into a lower surface of the pad insulation layer and electrically connected to the first redistribution structure; and a plurality of alignment patterns on an edge of the pad insulation layer, each of the plurality of alignment patterns including a first portion extending into a lower surface of the pad insulation layer and a second portion extending away from the lower surface of the pad insulation layer.

公开(公告)号：US20220208703A1

公开(公告)日：2022-06-30

申请号：US17697830

申请日：2022-03-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： JU-IL CHOI ,  UN-BYOUNG KANG ,  JIN HO AN ,  JONGHO LEE ,  JEONGGI JIN ,  ATSUSHI FUJISAKI

IPC: H01L23/00

Abstract: Semiconductor devices are provided. A semiconductor device includes an insulating layer and a conductive element in the insulating layer. The semiconductor device includes a first barrier pattern in contact with a surface of the conductive element and a surface of the insulating layer. The semiconductor device includes a second barrier pattern on the first barrier pattern. Moreover, the semiconductor device includes a metal pattern on the second barrier pattern. Related semiconductor packages are also provided.

公开(公告)号：US20220157702A1

公开(公告)日：2022-05-19

申请号：US17381869

申请日：2021-07-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： JU-IL CHOI ,  GYUHO KANG ,  SEONG-HOON BAE ,  JIN HO AN ,  JEONGGI JIN ,  ATSUSHI FUJISAKI

IPC: H01L23/498 ,  H01L25/065 ,  H01L25/10 ,  H01L23/538 ,  H01L23/00

Abstract: A semiconductor package may include a redistribution substrate, a semiconductor chip mounted on a top surface of the redistribution substrate, and a conductive terminal provided on a bottom surface of the redistribution substrate. The redistribution substrate may include an under-bump pattern including a via portion in contact with the conductive terminal and a wire portion on the via portion and an insulating layer covering top and side surfaces of the under-bump pattern. A central portion of a bottom surface of the via portion may be provided at a level higher than an edge portion of the bottom surface of the via portion.

公开(公告)号：US20250105116A1

公开(公告)日：2025-03-27

申请号：US18974377

申请日：2024-12-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： JU-IL CHOI ,  GYUHO KANG ,  SEONG-HOON BAE ,  JIN HO AN ,  JEONGGI JIN ,  ATSUSHI FUJISAKI

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10

Abstract: A semiconductor package may include a redistribution substrate, a semiconductor chip mounted on a top surface of the redistribution substrate, and a conductive terminal provided on a bottom surface of the redistribution substrate. The redistribution substrate may include an under-bump pattern including a via portion in contact with the conductive terminal and a wire portion on the via portion and an insulating layer covering top and side surfaces of the under-bump pattern. A central portion of a bottom surface of the via portion may be provided at a level higher than an edge portion of the bottom surface of the via portion.

公开(公告)号：US20230275052A1

公开(公告)日：2023-08-31

申请号：US18313560

申请日：2023-05-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： JU-IL CHOI ,  UN-BYOUNG KANG ,  JIN HO AN ,  JONGHO LEE ,  JEONGGI JIN ,  ATSUSHI FUJISAKI

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/03 ,  H01L2224/13113 ,  H01L2224/03614 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05016 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05144 ,  H01L2224/11849 ,  H01L2224/13026 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13155 ,  H01L2224/13144 ,  H01L2224/13139 ,  H01L2224/13147

Abstract: Semiconductor devices are provided. A semiconductor device includes an insulating layer and a conductive element in the insulating layer. The semiconductor device includes a first barrier pattern in contact with a surface of the conductive element and a surface of the insulating layer. The semiconductor device includes a second barrier pattern on the first barrier pattern. Moreover, the semiconductor device includes a metal pattern on the second barrier pattern. Related semiconductor packages are also provided.

公开(公告)号：US20140217559A1

公开(公告)日：2014-08-07

申请号：US14161034

申请日：2014-01-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： JU-IL CHOI ,  SU-KYOUNG KIM ,  KUN-SANG PARK ,  SEONG-MIN SON ,  JIN-HO AN ,  DO-SUN LEE

IPC: H01L23/522

CPC classification number: H01L23/5226 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/53295 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L25/0657 ,  H01L2224/02351 ,  H01L2224/03462 ,  H01L2224/0384 ,  H01L2224/0401 ,  H01L2224/05547 ,  H01L2224/05548 ,  H01L2224/05556 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/13 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/13027 ,  H01L2224/131 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

Abstract: A semiconductor device is provided having an insulating layer on a semiconductor substrate. The insulating layer and the semiconductor substrate define a through hole penetrating the semiconductor substrate and the insulating layer. A through electrode is provided in the through hole. A spacer is provided between the semiconductor substrate and the through electrode. An interconnection in continuity with the through electrode is provided on the insulating layer. A barrier layer covering a side and a bottom of the interconnection and a side of the through electrode is provided and the barrier layer is formed in one body.

Abstract translation: 提供了半导体器件，其在半导体衬底上具有绝缘层。 绝缘层和半导体衬底限定穿透半导体衬底和绝缘层的通孔。 通孔中设置有贯通电极。 在半导体衬底和贯通电极之间设置间隔物。 在绝缘层上设置与通孔电连接的互连。 设置覆盖互连的一侧和底部的阻挡层和通孔的一侧，并且阻挡层形成在一体中。

公开(公告)号：US20250087612A1

公开(公告)日：2025-03-13

申请号：US18626272

申请日：2024-04-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： JUNHYUN AN ,  UN-BYOUNG KANG ,  HYOJIN YUN ,  SEUNG HUN CHAE ,  JU-IL CHOI

IPC: H01L23/00

Abstract: The present disclosure relates to a conductive structure including: a conductive pad that includes a first seed layer having a first area and a second area surrounding the first area, and a first metal layer disposed on the first area of the first seed layer; and a conductive pillar disposed on the conductive pad, wherein a thickness of the conductive pad in an area vertically overlapping the first area of the first seed layer is thicker than a thickness of the conductive pad in an area vertically overlapping the second area of the first seed layer, a semiconductor chip including the conductive structure, and a manufacturing method of the conductive structure.

公开(公告)号：US20240250008A1

公开(公告)日：2024-07-25

申请号：US18453422

申请日：2023-08-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUSUK KANG ,  JU-IL CHOI ,  SUNG KEUN PARK ,  JONGHO PARK ,  HYUNJU LEE ,  JAEMOK JUNG

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10

CPC classification number: H01L23/49822 ,  H01L23/3107 ,  H01L23/49838 ,  H01L23/49866 ,  H01L24/16 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/35121

Abstract: A semiconductor package, comprising a redistribution substrate including an insulating layer and a first redistribution pattern; and a semiconductor chip electrically connected to the redistribution substrate, wherein the first redistribution pattern comprises a first barrier layer; a second barrier layer on the first barrier layer; and a via structure on the second barrier layer, wherein the first barrier layer comprises a first conductive material and the second barrier layer comprises a second conductive material different from the first conductive material.