公开(公告)号：US10900142B2

公开(公告)日：2021-01-26

申请号：US15641746

申请日：2017-07-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sam-mook Kang ,  Jun-youn Kim ,  Young-jo Tak ,  Mi-hyun Kim ,  Young-soo Park

IPC: C30B25/16 ,  H01L21/687 ,  H01J37/32 ,  C23C16/52 ,  C30B25/14 ,  C30B25/12 ,  C23C16/455 ,  C23C16/02 ,  C23C16/458 ,  C23C16/01 ,  C23C16/30 ,  C30B25/18 ,  C30B29/40 ,  H01L21/02 ,  H01L21/78

Abstract: An apparatus includes a deposition chamber housing that accommodates a growth substrate, a supply nozzle to supply a deposition gas for forming a target large-size substrate on the growth substrate into the deposition chamber housing, a susceptor to support the growth substrate and expose a rear surface of the growth substrate to an etch gas, and an inner liner connected to the susceptor. The inner liner is to isolate the etch gas from the deposition gas and guide the etch gas toward the rear surface of the growth substrate. The susceptor includes a center hole that exposes the rear surface of the growth substrate and a support protrusion supporting the growth substrate, the support protrusion protruding toward the center of the center hole from an inner sidewall of the susceptor defining the center hole.

公开(公告)号：US09472624B2

公开(公告)日：2016-10-18

申请号：US13837460

申请日：2013-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun-youn Kim ,  Joo-sung Kim ,  Moon-seung Yang

IPC: H01L29/20 ,  H01L21/02 ,  H01L29/267

CPC classification number: H01L29/2003 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/02507 ,  H01L21/0251 ,  H01L21/0254 ,  H01L29/267

Abstract: A semiconductor structure including a first nitride semiconductor layer, a second nitride semiconductor layer, and a third layer between the first nitride semiconductor layer and the second nitride semiconductor layer. The first nitride semiconductor layer has a first gallium composition ratio, the second nitride semiconductor layer has a second gallium composition ratio different from the first metal composition ratio, and the third layer has a third gallium composition ratio greater than at least one of the first gallium composition ratio or the second gallium composition ratio. The structure may also include a fourth layer for reducing tensile stress or increasing compression stress experienced by at least the second nitride semiconductor layer.

Abstract translation: 一种在第一氮化物半导体层和第二氮化物半导体层之间包括第一氮化物半导体层，第二氮化物半导体层和第三层的半导体结构。 第一氮化物半导体层具有第一镓组成比，第二氮化物半导体层具有与第一金属组成比不同的第二镓组成比，并且第三层具有大于第一镓的至少一种的第三镓组成比 组成比或第二镓组成比。 该结构还可以包括用于降低至少第二氮化物半导体层所经历的拉伸应力或增加压缩应力的第四层。

公开(公告)号：US09246048B2

公开(公告)日：2016-01-26

申请号：US14564928

申请日：2014-12-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Su-hee Chae ,  Young-soo Park ,  Bok-ki Min ,  Jun-youn Kim ,  Hyun-gi Hong

IPC: H01L21/00 ,  H01L33/00 ,  H01L33/38 ,  H01L33/12 ,  H01L33/24 ,  H01L33/22 ,  H01L33/40

CPC classification number: H01L33/0066 ,  H01L33/0075 ,  H01L33/0079 ,  H01L33/12 ,  H01L33/22 ,  H01L33/24 ,  H01L33/382 ,  H01L33/405 ,  H01L2933/0016

Abstract: Example embodiments are directed to light-emitting devices (LEDs) and methods of manufacturing the same. The LED includes a first semiconductor layer; a second semiconductor layer; an active layer formed between the first and second semiconductor layers; and an emission pattern layer including a plurality of layers on the first semiconductor layer, the emission pattern including an emission pattern for externally emitting light generated from the active layer.

公开(公告)号：US08877652B2

公开(公告)日：2014-11-04

申请号：US14146233

申请日：2014-01-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun-youn Kim ,  Su-hee Chae ,  Hyun-gi Hong ,  Young-jo Tak

IPC: H01L33/12 ,  H01L21/02 ,  H01L33/00 ,  H01S5/00 ,  H01S5/02 ,  H01S5/323

CPC classification number: H01L21/02658 ,  H01L21/0237 ,  H01L21/0242 ,  H01L21/02494 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/0265 ,  H01L33/0079 ,  H01L33/12 ,  H01S5/005 ,  H01S5/0207 ,  H01S5/32341

Abstract: A substrate structure and method of manufacturing the same are disclosed. The substrate structure may includes a substrate on which a plurality of protrusions are formed on one surface thereof and a plurality of buffer layers formed according to a predetermined pattern and formed spaced apart from each other on the plurality of protrusions.

公开(公告)号：US09449817B2

公开(公告)日：2016-09-20

申请号：US14586048

申请日：2014-12-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-jo Tak ,  Jae-won Lee ,  Young-soo Park ,  Jun-youn Kim

IPC: H01L21/20 ,  H01L21/02 ,  H01L33/00 ,  H01L33/12 ,  H01L33/32

CPC classification number: H01L21/0254 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/02505 ,  H01L21/02507 ,  H01L21/0259 ,  H01L21/02642 ,  H01L21/02664 ,  H01L33/007 ,  H01L33/12 ,  H01L33/32

Abstract: A semiconductor device includes a substrate, a buffer layer on the substrate, and a plurality of nitride semiconductor layers on the buffer layer. The semiconductor device further includes at least one masking layer and at least one inter layer between the plurality of nitride semiconductor layers. The at least one inter layer is on the at least one masking layer.

公开(公告)号：US08901598B2

公开(公告)日：2014-12-02

申请号：US13856716

申请日：2013-04-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun-sik Hwang ,  Jun-youn Kim ,  Su-hee Chae

IPC: H01L33/00 ,  H01L33/12

CPC classification number: H01L33/0079 ,  H01L33/12

Abstract: A light emitting device (LED) includes a stress control layer having a compressive stress on a substrate, a bonding layer on the stress control layer, a semiconductor layer on the bonding layer and including an active region for emitting light on the bonding layer, a first electrode on a lower surface of the substrate, and a second electrode on the semiconductor layer. The compressive stress of the stress control layer is between about 1 and about 20 GPa.

Abstract translation: 发光器件（LED）包括在基板上具有压应力的应力控制层，应力控制层上的接合层，接合层上的半导体层，并且包括用于在接合层上发光的有源区， 在基板的下表面上的第一电极和在半导体层上的第二电极。 应力控制层的压缩应力在约1和约20GPa之间。

公开(公告)号：US09202878B2

公开(公告)日：2015-12-01

申请号：US13713415

申请日：2012-12-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-jo Tak ,  Jae-kyun Kim ,  Jun-youn Kim ,  Jae-won Lee ,  Hyo-ji Choi

IPC: H01L29/15 ,  H01L31/0256 ,  H01L29/267 ,  H01L29/20 ,  H01L21/02 ,  H01L29/16 ,  H01L33/12 ,  H01L33/00

CPC classification number: H01L29/267 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/02458 ,  H01L21/02488 ,  H01L21/0254 ,  H01L29/16 ,  H01L29/2003 ,  H01L33/007 ,  H01L33/12

Abstract: A gallium nitride based semiconductor device includes a silicon-based layer doped simultaneously with boron (B) and germanium (Ge) at a relatively high concentration, a buffer layer on the silicon-based layer, and a nitride stack on the buffer layer. A doping concentration of boron (B) and germanium (Ge) may be higher than 1×1019/cm3.

Abstract translation: 氮化镓基半导体器件包括以相对高的浓度与硼（B）和锗（Ge）同时掺杂的硅基层，硅基层上的缓冲层和缓冲层上的氮化物叠层。 硼（B）和锗（Ge）的掺杂浓度可高于1×1019 / cm3。

公开(公告)号：US09190270B2

公开(公告)日：2015-11-17

申请号：US14294823

申请日：2014-06-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-jo Tak ,  Jae-kyun Kim ,  Joo-sung Kim ,  Jun-youn Kim ,  Young-soo Park ,  Eun-ha Lee

IPC: H01L21/02 ,  H01L33/00 ,  H01L33/12 ,  H01L33/32 ,  H01S5/00 ,  H01S5/02 ,  H01S5/343

CPC classification number: H01L21/0254 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02505 ,  H01L33/007 ,  H01L33/12 ,  H01L33/325 ,  H01S5/0014 ,  H01S5/021 ,  H01S5/34333

Abstract: Provided are a low-defect semiconductor device and a method of manufacturing the same. The method includes forming a buffer layer on a silicon substrate, forming an interface control layer on the buffer layer under a first growth condition, and forming a nitride stack on the interface control layer under a second growth condition different from the first growth condition.

Abstract translation: 提供了一种低缺陷半导体器件及其制造方法。 该方法包括在硅衬底上形成缓冲层，在第一生长条件下在缓冲层上形成界面控制层，并在不同于第一生长条件的第二生长条件下，在界面控制层上形成氮化层。

公开(公告)号：US08946773B2

公开(公告)日：2015-02-03

申请号：US13835704

申请日：2013-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-jo Tak ,  Jae-kyun Kim ,  Joo-sung Kim ,  Jun-youn Kim ,  Jae-won Lee ,  Hyo-ji Choi

IPC: H01L29/267 ,  H01L21/02 ,  H01L29/20

CPC classification number: H01L29/267 ,  G11C11/161 ,  H01L21/02104 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/02507 ,  H01L21/0251 ,  H01L21/0254 ,  H01L29/2003

Abstract: A semiconductor buffer structure may include a silicon substrate and a buffer layer that is formed on the silicon substrate. The buffer layer may include a first layer, a second layer formed on the first layer, and a third layer formed on the second layer. The first layer may include AlxInyGa1-x-yN (0≦x≦1, 0≦y≦1, 0≦x+y≦1) and have a lattice constant LP1 that is smaller than a lattice constant LP0 of the silicon substrate. The second layer may include AlxInyGa1-x-yN (0≦x

Abstract translation: 半导体缓冲结构可以包括硅衬底和形成在硅衬底上的缓冲层。 缓冲层可以包括第一层，形成在第一层上的第二层和形成在第二层上的第三层。 第一层可以包括比硅衬底的晶格常数LP0小的晶格常数LP1的Al x In y Ga 1-x-y N（0＆n 1; x＆n 1; 1,0＆amp; n 1; y＆n 1 E; 1,0＆ 第二层可以包括Al x In y Ga 1-x-y N（0＆nlE; x <1,0＆lt; nlE; y <1,0＆amp; nlE; x + y <1），并且具有大于晶格常数LP1并且小于晶格的晶格常数LP2 常数LP0。 第三层可以包括Al x In y Ga 1-x-y N（0＆nlE; x <1,0＆lt; nlE; y <1,0＆amp; nlE; x + y <1），并且具有大于晶格常数LP1并且小于晶格的晶格常数LP3 常数LP2。

公开(公告)号：US08871544B2

公开(公告)日：2014-10-28

申请号：US14067185

申请日：2013-10-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyung-su Jeong ,  Young-soo Park ,  Su-hee Chae ,  Bok-ki Min ,  Jun-youn Kim ,  Hyun-gi Hong ,  Young-jo Tak ,  Jae-won Lee

IPC: H01L21/00 ,  H01L33/00 ,  H01L33/32 ,  H01L27/15 ,  H01L33/38 ,  H01L33/42

CPC classification number: H01L33/0025 ,  H01L27/156 ,  H01L33/32 ,  H01L33/38 ,  H01L33/42

Abstract: Example embodiments are directed to a light-emitting device including a patterned emitting unit and a method of manufacturing the light-emitting device. The light-emitting device includes a first electrode on a top of a semiconductor layer, and a second electrode on a bottom of the semiconductor layer, wherein the semiconductor layer is a pattern array formed of a plurality of stacks. A space between the plurality of stacks is filled with an insulating layer, and the first electrode is on the insulating layer.

Abstract translation: 示例性实施例涉及包括图案化发光单元的发光器件和制造发光器件的方法。 发光器件包括在半导体层的顶部上的第一电极和在半导体层的底部上的第二电极，其中半导体层是由多个堆叠形成的图案阵列。 多个堆叠之间的空间填充有绝缘层，并且第一电极在绝缘层上。