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    SEMICONDUCTOR DEVICE
    1.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20190067228A1

    公开(公告)日：2019-02-28

    申请号：US16052383

    申请日：2018-08-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seong-Min SON ,  Jeong-Gi JIN ,  Jin-Ho AN ,  Jin-Ho CHUN ,  Kwang-Jin MOON ,  Ho-Jin LEE

    IPC: H01L23/00 ,  H01L23/522 ,  H01L23/485

    Abstract: A semiconductor device includes a protective layer, a redistribution pattern, a pad pattern and an insulating polymer layer. The protective layer may be formed on a substrate. The redistribution pattern may be formed on the protective layer. An upper surface of the redistribution may be substantially flat. The pad pattern may be formed directly on the redistribution pattern. An upper surface of the pad pattern may be substantially flat. The insulating polymer layer may be formed on the redistribution pattern and the pad pattern. An upper surface of the insulating polymer layer may be lower than the upper surface of the pad pattern. The semiconductor device may have a high reliability.

    SEMICONDUCTOR DEVICES
    2.
    发明申请
    SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20200006269A1

    公开(公告)日：2020-01-02

    申请号：US16562434

    申请日：2019-09-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yi-Koan HONG ,  Kwang-Jin MOON ,  Nae-In LEE ,  Ho-Jin LEE

    IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

    Abstract: A semiconductor device includes a first conductive pattern at an upper portion of a first insulating interlayer on a first substrate, a first plurality of conductive nanotubes (CNTs) extending vertically, a second conductive pattern at a lower portion of a second insulating interlayer beneath a second substrate, and a second plurality of CNTs extending vertically. A lower surface of the second insulating interlayer contacts an upper surface of the first insulating interlayer. At least a portion of a sidewall of each of the first plurality of CNTs is covered by the first conductive pattern, and at least a portion of a sidewall of each of the second plurality of CNTs is covered by the second conductive pattern. The first and second conductive patterns vertically face each other, and at least one of the first plurality of CNTs and at least one of the second plurality of CNTs contact each other.

    SEMICONDUCTOR DEVICE
    5.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20210005565A1

    公开(公告)日：2021-01-07

    申请号：US17029639

    申请日：2020-09-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seong-Min SON ,  Jeong-Gi JIN ,  Jin-Ho AN ,  Jin-Ho CHUN ,  Kwang-Jin MOON ,  Ho-Jin LEE

    IPC: H01L23/00 ,  H01L23/485 ,  H01L23/522

    Abstract: A semiconductor device includes a protective layer, a redistribution pattern, a pad pattern and an insulating polymer layer. The protective layer may be formed on a substrate. The redistribution pattern may be formed on the protective layer. An upper surface of the redistribution may be substantially flat. The pad pattern may be formed directly on the redistribution pattern. An upper surface of the pad pattern may be substantially flat. The insulating polymer layer may be formed on the redistribution pattern and the pad pattern. An upper surface of the insulating polymer layer may be lower than the upper surface of the pad pattern. The semiconductor device may have a high reliability.

    METHODS OF FORMING A SEMICONDUCTOR DEVICE
    9.
    发明申请
    METHODS OF FORMING A SEMICONDUCTOR DEVICE 审中-公开
    形成半导体器件的方法

    公开(公告)号：US20130337647A1

    公开(公告)日：2013-12-19

    申请号：US13971991

    申请日：2013-08-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Deok-Young JUNG ,  Gil-Heyun CHOI ,  Suk-Chul BANG ,  Byung-Lyul PARK ,  Kwang-Jin MOON ,  Dong-Chan LIM

    IPC: H01L21/768

    CPC classification number: H01L21/76802 ,  H01L21/02057 ,  H01L21/30655 ,  H01L21/76814 ,  H01L21/76898

    Abstract: The methods include forming a semiconductor substrate pattern by etching a semiconductor substrate. The semiconductor pattern has a first via hole that exposes side walls of the semiconductor substrate pattern, and the side walls of the semiconductor substrate pattern exposed by the first via hole have an impurity layer pattern. The methods further include treating upper surfaces of the semiconductor substrate pattern, the treated upper surfaces of the semiconductor substrate pattern being hydrophobic; removing the impurity layer pattern from the side walls of the semiconductor substrate pattern exposed by the first via hole; forming a first insulating layer pattern on the side walls of the semiconductor substrate pattern exposed by the first via hole; and filling a first conductive layer pattern into the first via hole and over the first insulating layer pattern.

    Abstract translation: 所述方法包括通过蚀刻半导体衬底形成半导体衬底图案。 半导体图案具有暴露半导体衬底图案的侧壁的第一通孔，并且由第一通孔露出的半导体衬底图案的侧壁具有杂质层图案。 所述方法还包括处理半导体衬底图案的上表面，所处理的半导体衬底图案的上表面是疏水的; 从由第一通孔露出的半导体衬底图案的侧壁去除杂质层图案; 在由第一通孔露出的半导体衬底图案的侧壁上形成第一绝缘层图案; 以及将第一导电层图案填充到第一通孔中并在第一绝缘层图案之上。

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