公开(公告)号：US09461007B2

公开(公告)日：2016-10-04

申请号：US14796506

申请日：2015-07-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-ho Chun ,  Pil-kyu Kang ,  Byung-lyul Park ,  Jae-hwa Park ,  Ju-il Choi

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/532 ,  H01L23/31 ,  H01L25/00

CPC classification number: H01L24/08 ,  H01L23/3192 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53295 ,  H01L24/05 ,  H01L24/80 ,  H01L24/94 ,  H01L25/50 ,  H01L2224/05025 ,  H01L2224/05147 ,  H01L2224/05546 ,  H01L2224/05547 ,  H01L2224/05647 ,  H01L2224/0569 ,  H01L2224/08145 ,  H01L2224/80862 ,  H01L2224/80895 ,  H01L2224/80905 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06548 ,  H01L2924/06 ,  H01L2924/0695 ,  H01L2924/07025 ,  H01L2224/80 ,  H01L2924/00014

Abstract: A wafer-to-wafer bonding structure may include: a first wafer including a first insulating layer on a first substrate and on a first copper (Cu) pad that penetrates the first insulating layer and has portions protruding from an upper surface of the first insulating layer, and a first barrier metal layer on a lower surface and sides of the first Cu pad; a second wafer including a second insulating layer on a second substrate and on a second copper (Cu) pad that penetrates the second insulating layer, has portions protruding from an upper surface of the second insulating layer, and is bonded to the first Cu pad, and a second barrier metal layer on a lower surface and sides of the second Cu pad; and a polymer layer covering protruding sides of the first and second barrier metal layers and disposed between the first and second wafers.

Abstract translation: 晶片到晶片接合结构可以包括：第一晶片，其包括在第一基板上的第一绝缘层和穿过第一绝缘层的第一铜（Cu）焊盘，并且具有从第一绝缘层的上表面突出的部分 层和第一Cu衬垫的下表面和侧面上的第一阻挡金属层; 包括在第二基板上的第二绝缘层和穿过第二绝缘层的第二铜（Cu）焊盘上的第二晶片具有从第二绝缘层的上表面突出的部分并且接合到第一Cu焊盘， 以及在所述第二Cu垫的下表面和侧面上的第二阻挡金属层; 以及覆盖第一和第二阻挡金属层的突出侧并设置在第一和第二晶片之间的聚合物层。

公开(公告)号：US20140110894A1

公开(公告)日：2014-04-24

申请号：US13964433

申请日：2013-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho-Jin Lee ,  Pil-kyu Kang ,  Taeyeong Kim ,  Byung Lyul Park ,  Kyu-Ha Lee ,  Gilheyun Choi

IPC: H01L21/683

CPC classification number: H01L21/6835 ,  H01L24/03 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/92 ,  H01L24/94 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/92 ,  H01L2224/9222 ,  H01L2224/92222 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/15311 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2221/68304 ,  H01L21/304 ,  H01L2221/68381 ,  H01L21/78 ,  H01L2224/81

Abstract: A wafer carrier includes a base having a cavity provided at the center of the base and an outer sidewall extending along and away from an edge of the base to define the cavity. The cavity is configured to be filled with an adhesive layer. The wafer carrier is configured to be bonded to a wafer with an adhesive layer in the cavity of base such that the outer sidewall faces and is in contact with an edge of the wafer and the cavity faces a center of the wafer.

Abstract translation: 晶片载体包括具有设置在基部的中心处的空腔的基部和沿着基部的边缘延伸并远离基部的边缘的外侧壁以限定空腔。 空腔构造成填充有粘合剂层。 晶片载体构造成在基底的空腔中与粘合剂层结合到晶片，使得外侧壁面向并与晶片的边缘接触并且空腔面向晶片的中心。

公开(公告)号：US09941243B2

公开(公告)日：2018-04-10

申请号：US15413824

申请日：2017-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-yeong Kim ,  Pil-kyu Kang ,  Seok-ho Kim ,  Kwang-jin Moon ,  Ho-jin Lee

IPC: H01L23/52 ,  H01L23/00

CPC classification number: H01L24/94 ,  H01L24/02 ,  H01L24/05 ,  H01L24/29 ,  H01L24/80 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/02215 ,  H01L2224/04105 ,  H01L2224/05147 ,  H01L2224/29187 ,  H01L2224/29188 ,  H01L2224/8012 ,  H01L2224/8312 ,  H01L2224/83896 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2924/0537 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/0549 ,  H01L2924/365 ,  H01L2224/80

Abstract: A wafer-to-wafer bonding structure includes a first wafer including a first conductive pad in a first insulating layer and a first barrier layer surrounding a lower surface and side surfaces of the first conductive pad, a second wafer including a second conductive pad in a second insulating layer and a second barrier layer surrounding a lower surface and side surfaces of the second conductive pad, the second insulating layer being bonded to the first insulating layer, and at least a portion of an upper surface of the second conductive pad being partially or entirely bonded to at least a portion of an upper surface of the first conductive pad, and a third barrier layer between portions of the first and second wafers where the first and second conductive pads are not bonded to each other.

公开(公告)号：US09831164B2

公开(公告)日：2017-11-28

申请号：US13756593

申请日：2013-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwang-jin Moon ,  Pil-kyu Kang ,  Dae-lok Bae ,  Gil-heyun Choi ,  Byung-lyul Park ,  Dong-chan Lim ,  Deok-young Jung

IPC: H01L23/48 ,  H01L23/498 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/49827 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a via structure and a conductive structure. The via structure has a surface with a planar portion and a protrusion portion. The conductive structure is formed over at least part of the planar portion and not over at least part of the protrusion portion of the via structure. For example, the conductive structure is formed only onto the planar portion and not onto any of the protrusion portion for forming high quality connection between the conductive structure and the via structure.

公开(公告)号：US20160013160A1

公开(公告)日：2016-01-14

申请号：US14796506

申请日：2015-07-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-ho CHUN ,  Pil-kyu Kang ,  Byung-Iyul Park ,  Jae-hwa Park ,  Ju-il Choi

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L24/08 ,  H01L23/3192 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53295 ,  H01L24/05 ,  H01L24/80 ,  H01L24/94 ,  H01L25/50 ,  H01L2224/05025 ,  H01L2224/05147 ,  H01L2224/05546 ,  H01L2224/05547 ,  H01L2224/05647 ,  H01L2224/0569 ,  H01L2224/08145 ,  H01L2224/80862 ,  H01L2224/80895 ,  H01L2224/80905 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06548 ,  H01L2924/06 ,  H01L2924/0695 ,  H01L2924/07025 ,  H01L2224/80 ,  H01L2924/00014

Abstract: A wafer-to-wafer bonding structure may include: a first wafer including a first insulating layer on a first substrate and on a first copper (Cu) pad that penetrates the first insulating layer and has portions protruding from an upper surface of the first insulating layer, and a first barrier metal layer on a lower surface and sides of the first Cu pad; a second wafer including a second insulating layer on a second substrate and on a second copper (Cu) pad that penetrates the second insulating layer, has portions protruding from an upper surface of the second insulating layer, and is bonded to the first Cu pad, and a second barrier metal layer on a lower surface and sides of the second Cu pad; and a polymer layer covering protruding sides of the first and second barrier metal layers and disposed between the first and second wafers.

Abstract translation: 晶片到晶片接合结构可以包括：第一晶片，其包括在第一基板上的第一绝缘层和穿过第一绝缘层的第一铜（Cu）焊盘，并且具有从第一绝缘层的上表面突出的部分 层和第一Cu衬垫的下表面和侧面上的第一阻挡金属层; 包括在第二基板上的第二绝缘层和穿过第二绝缘层的第二铜（Cu）焊盘上的第二晶片具有从第二绝缘层的上表面突出的部分并且接合到第一Cu焊盘， 以及在所述第二Cu垫的下表面和侧面上的第二阻挡金属层; 以及覆盖第一和第二阻挡金属层的突出侧并设置在第一和第二晶片之间的聚合物层。

公开(公告)号：US09583373B2

公开(公告)日：2017-02-28

申请号：US13964433

申请日：2013-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho-Jin Lee ,  Pil-kyu Kang ,  Taeyeong Kim ,  Byung Lyul Park ,  Kyu-Ha Lee ,  Gilheyun Choi

IPC: H01L21/683 ,  H01L23/00

CPC classification number: H01L21/6835 ,  H01L24/03 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/92 ,  H01L24/94 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/92 ,  H01L2224/9222 ,  H01L2224/92222 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/15311 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2221/68304 ,  H01L21/304 ,  H01L2221/68381 ,  H01L21/78 ,  H01L2224/81

Abstract: A wafer carrier includes a base having a cavity provided at the center of the base and an outer sidewall extending along and away from an edge of the base to define the cavity. The cavity is configured to be filled with an adhesive layer. The wafer carrier is configured to be bonded to a wafer with an adhesive layer in the cavity of base such that the outer sidewall faces and is in contact with an edge of the wafer and the cavity faces a center of the wafer.

Abstract translation: 晶片载体包括具有设置在基部的中心处的空腔的基部和沿着基部的边缘延伸并远离基部的边缘的外侧壁以限定空腔。 空腔构造成填充有粘合剂层。 晶片载体构造成在基底的空腔中与粘合剂层结合到晶片，使得外侧壁面向并与晶片的边缘接触并且空腔面向晶片的中心。

公开(公告)号：US20180370210A1

公开(公告)日：2018-12-27

申请号：US15845458

申请日：2017-12-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-yeong Kim ,  Pil-kyu Kang ,  Seok-ho Kim ,  Kwang-jin Moon ,  Na-ein Lee ,  Ho-jin Lee

IPC: B32B37/10 ,  H01L21/67 ,  H01L21/687 ,  H01L21/68 ,  H01L23/00

Abstract: Provided are a wafer bonding apparatus for accurately detecting a bonding state of wafers in a wafer bonding process and/or in a wafer bonding system including the wafer bonding apparatus. The wafer bonding apparatus includes a first supporting plate including a first surface and vacuum grooves for vacuum-absorption of a first wafer disposed on the first surface, a second supporting plate including a second surface facing the first surface. A second wafer is on the second surface. The wafer bonding apparatus and/or the wafer bonding system include a bonding initiator at a center portion of the first supporting plate, and an area sensor on the first supporting plate and configured to detect a propagation state of bonding between the first wafer and the second wafer.

公开(公告)号：US09935037B2

公开(公告)日：2018-04-03

申请号：US15408977

申请日：2017-01-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Pil-kyu Kang ,  Ho-jin Lee ,  Byung-lyul Park ,  Tae-yeong Kim ,  Seok-ho Kim

IPC: H01L23/48 ,  H01L21/768 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/481 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/09 ,  H01L24/17 ,  H01L25/0657 ,  H01L2224/08146 ,  H01L2224/16146 ,  H01L2225/06548

Abstract: A multi-stacked device includes a lower device having a lower substrate, a first insulating layer on the lower substrate, and a through-silicon-via (TSV) pad on the first insulating layer, an intermediate device having an intermediate substrate, a second insulating layer on the intermediate substrate, and a first TSV bump on the second insulating layer, an upper device having an upper substrate, a third insulating layer on the upper substrate, a second TSV bump on the third insulating layer, and a TSV structure passing through the upper substrate, the third insulating layer, the second insulating layer, and the intermediate substrate to be connected to the first TSV bump, the second TSV bump, and the TSV pad. An insulating first TSV spacer between the intermediate substrate and the TSV structure and an insulating second TSV spacer between the upper substrate and the TSV structure are spaced apart along a stacking direction.

公开(公告)号：US09773660B2

公开(公告)日：2017-09-26

申请号：US14056270

申请日：2013-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-yeong Kim ,  Pil-kyu Kang ,  Byung-lyul Park ,  Jin-ho Park

IPC: H01L21/02 ,  H01L21/30 ,  H01L21/68 ,  H01L21/304 ,  H01L21/683

CPC classification number: H01L21/02016 ,  H01L21/304 ,  H01L21/6835 ,  H01L21/6836 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2221/68381

Abstract: Wafer processing methods are provided. The methods may include cutting respective edges of a wafer and an adhesive a predetermined angle before grinding a back surface of the wafer.