公开(公告)号：US20180247891A1

公开(公告)日：2018-08-30

申请号：US15968093

申请日：2018-05-01

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Shih-Chao Chiu ,  Chun-Hsien Lin ,  Ming-Chen Sun ,  Yu-Cheng Pai ,  Tzu-Chieh Shen

IPC: H01L23/522

CPC classification number: H01L23/5226 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2224/1703 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/92242 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/15153 ,  H01L2924/15313 ,  H01L2924/1579 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/014

Abstract: A method of fabricating a semiconductor package is provided, including providing a carrier provided having a circuit layer and a blocking member, forming on the carrier an encapsulating layer having a first surface and a second surface opposing the first surface and encapsulating the circuit layer and the blocking member, with the first surface coupled with the carrier, and removing the carrier and the blocking member to form in the encapsulating layer via the first surface thereof an opening for an electronic component to be received therein. Before the electronic component is disposed in the opening, the circuit layer and the electronic component can be tested in advance, in order to retire the defectives. Therefore, as a defective electronic component is prevented from being disposed in the opening, no defective semiconductor package will be fabricated.

公开(公告)号：US20170309537A1

公开(公告)日：2017-10-26

申请号：US15648089

申请日：2017-07-12

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Shih-Chao Chiu ,  Chun-Hsien Lin ,  Yu-Cheng Pai ,  Wei-Chung Hsiao ,  Ming-Chen Sun ,  Tzu-Chieh Shen ,  Chia-Cheng Chen

IPC: H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L23/49861 ,  H01L21/4846 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49827 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A single-layer wiring package substrate and a method of fabricating the same are provided, the method including: forming on a carrier a wiring layer having a first surface and a second surface opposing the first surface and being in contact with the carrier; forming on the carrier and on the wiring layer a dielectric body that has a first side having a first opening, from which a portion of the wiring layer is exposed, and a second side opposing the first side and disposed at the same side as the second surface of the wiring layer; and removing the carrier, with the second side of the dielectric body and the second surface of the wiring layer exposed. Therefore, a coreless package substrate is fabricated, and the overall thickness and cost of the substrate are reduced.

公开(公告)号：US09716060B2

公开(公告)日：2017-07-25

申请号：US14692769

申请日：2015-04-22

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Shih-Chao Chiu ,  Chun-Hsien Lin ,  Yu-Cheng Pai ,  Wei-Chung Hsiao ,  Ming-Chen Sun ,  Tzu-Chieh Shen ,  Chia-Cheng Chen

IPC: H01L23/498 ,  H05K3/00 ,  H05K3/32 ,  H05K1/18 ,  H01L23/538 ,  H01L23/00 ,  H05K1/02 ,  H05K3/10 ,  H05K3/46 ,  H01L23/31 ,  H01L21/683

CPC classification number: H01L23/49838 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2221/68318 ,  H01L2221/68345 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32058 ,  H01L2224/32105 ,  H01L2224/32106 ,  H01L2224/32237 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/83101 ,  H01L2924/15313 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/19104 ,  H05K1/0231 ,  H05K1/185 ,  H05K1/186 ,  H05K1/189 ,  H05K3/0026 ,  H05K3/007 ,  H05K3/108 ,  H05K3/32 ,  H05K3/4682 ,  H05K2201/0376 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10674 ,  H05K2201/10977 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/0665

Abstract: The present invention provides a package structure with an embedded electronic component and a method of fabricating the package structure. The method includes: forming a first wiring layer on a carrier; removing the carrier and forming the first wiring layer on a bonding carrier; disposing an electronic component on the first wiring layer; forming an encapsulating layer, a second wiring layer and an insulating layer on the first wiring layer; disposing a chip on the electronic component and the second wiring layer; and forming a covering layer that covers the chip. The present invention can effectively reduce the thickness of the package structure and the electronic component without using adhesives.

公开(公告)号：US20160163621A1

公开(公告)日：2016-06-09

申请号：US14876404

申请日：2015-10-06

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Shih-Chao Chiu ,  Chun-Hsien Lin ,  Yu-Cheng Pai ,  Wei-Chung Hsiao ,  Ming-Chen Sun ,  Tzu-Chieh Shen ,  Chia-Cheng Chen

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/31 ,  H01L21/48

CPC classification number: H01L23/49861 ,  H01L21/4846 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49827 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A single-layer wiring package substrate and a method of fabricating the same are provided, the method including: forming on a carrier a wiring layer having a first surface and a second surface opposing the first surface and being in contact with the carrier; forming on the carrier and on the wiring layer a dielectric body that has a first side having a first opening, from which a portion of the wiring layer is exposed, and a second side opposing the first side and disposed at the same side as the second surface of the wiring layer; and removing the carrier, with the second side of the dielectric body and the second surface of the wiring layer exposed. Therefore, a coreless package substrate is fabricated, and the overall thickness and cost of the substrate are reduced.

Abstract translation: 提供一种单层布线封装基板及其制造方法，该方法包括：在载体上形成具有与第一表面相对并与载体接触的第一表面和第二表面的布线层; 在所述载体上和所述布线层上形成绝缘体，所述绝缘体具有第一侧面，所述第一侧面具有第一开口，所述布线层的一部分从该第一开口露出;以及与所述第一侧相对的第二侧， 布线层表面; 并且在绝缘体的第二面和布线层的第二表面露出的同时移除载体。 因此，制造无芯封装基板，并且减小基板的整体厚度和成本。

公开(公告)号：US20160079170A1

公开(公告)日：2016-03-17

申请号：US14708249

申请日：2015-05-10

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yu-Cheng Pai ,  Wei-Chung Hsiao ,  Shih-Chao Chiu ,  Chun-Hsien Lin ,  Ming-Chen Sun ,  Tzu-Chieh Shen ,  Chia-Cheng Chen

IPC: H01L23/538 ,  H01L21/56 ,  H01L21/48 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/5389 ,  H01L21/568 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2224/81

Abstract: A semiconductor package structure and a method of fabricating the same are provided. The semiconductor package structure includes a package body having opposing first and second surfaces; a plurality of first conductive pads and a plurality of second conductive pads formed on the first surface of the package body; a semiconductor component embedded in the package body and electrically connected to the first conductive pads; and a plurality of conductive elements embedded in the package body, each of the conductive elements having a first end electrically connected to a corresponding one of the second conductive pads and a second end opposing the first end and exposed from the second surface of the package body. Since the semiconductor component is embedded in the package body, the thickness of the semiconductor package structure is reduced.

Abstract translation: 提供半导体封装结构及其制造方法。 半导体封装结构包括具有相对的第一和第二表面的封装体; 多个第一导电焊盘和形成在封装主体的第一表面上的多个第二导电焊盘; 嵌入在所述封装主体中并电连接到所述第一导电焊盘的半导体部件; 以及嵌入在所述封装主体中的多个导电元件，每个所述导电元件具有电连接到所述第二导电焊盘中的相应一个的第一端和与所述第一端相对并从所述封装体的所述第二表面露出的第二端 。 由于半导体部件嵌入封装主体中，所以半导体封装结构的厚度减小。

公开(公告)号：US10043757B2

公开(公告)日：2018-08-07

申请号：US14708249

申请日：2015-05-10

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yu-Cheng Pai ,  Wei-Chung Hsiao ,  Shih-Chao Chiu ,  Chun-Hsien Lin ,  Ming-Chen Sun ,  Tzu-Chieh Shen ,  Chia-Cheng Chen

IPC: H01L29/40 ,  H01L23/538 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31

Abstract: A semiconductor package structure and a method of fabricating the same are provided. The semiconductor package structure includes a package body having opposing first and second surfaces; a plurality of first conductive pads and a plurality of second conductive pads formed on the first surface of the package body; a semiconductor component embedded in the package body and electrically connected to the first conductive pads; and a plurality of conductive elements embedded in the package body, each of the conductive elements having a first end electrically connected to a corresponding one of the second conductive pads and a second end opposing the first end and exposed from the second surface of the package body. Since the semiconductor component is embedded in the package body, the thickness of the semiconductor package structure is reduced.

公开(公告)号：US20170236725A1

公开(公告)日：2017-08-17

申请号：US15466063

申请日：2017-03-22

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Ming-Chen Sun ,  Chun-Hsien Lin ,  Tzu-Chieh Shen ,  Shih-Chao Chiu ,  Yu-Cheng Pai

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L21/4853 ,  H01L21/486 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/8182 ,  H01L2924/15313 ,  H05K1/111 ,  H05K3/20 ,  H05K3/205 ,  H05K3/428 ,  H05K2201/0376 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2201/10674 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A package substrate and a semiconductor package are provided. The package substrate includes an insulating layer having opposing first and second surfaces; a first wiring layer formed in the insulating layer, exposed from the first surface of the insulating layer, and having a plurality of first conductive pads; a second wiring layer formed in the insulating layer, exposed from the second surface, and having a plurality of second conductive pads; a third wiring layer formed on the first surface and electrically connected with the first wiring layer; a plurality of first metal bumps formed on the first conductive pads corresponding; and at least one conductive via vertically embedded in the insulating layer and electrically connected to the second and third wiring layers. Therefore, the surfaces of first conductive pads are reduced, and the non-wetting between the first conductive pads and the solder materials formed on conductive bumps is avoided.

公开(公告)号：US20160079151A1

公开(公告)日：2016-03-17

申请号：US14692769

申请日：2015-04-22

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Shih-Chao Chiu ,  Chun-Hsien Lin ,  Yu-Cheng Pai ,  Wei-Chung Hsiao ,  Ming-Chen Sun ,  Tzu-Chieh Shen ,  Chia-Cheng Chen

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/683 ,  H01L23/31 ,  H05K1/18 ,  H05K3/00 ,  H01L23/538 ,  H01L21/56 ,  H01L23/00 ,  H05K3/32

CPC classification number: H01L23/49838 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2221/68318 ,  H01L2221/68345 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32058 ,  H01L2224/32105 ,  H01L2224/32106 ,  H01L2224/32237 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/83101 ,  H01L2924/15313 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/19104 ,  H05K1/0231 ,  H05K1/185 ,  H05K1/186 ,  H05K1/189 ,  H05K3/0026 ,  H05K3/007 ,  H05K3/108 ,  H05K3/32 ,  H05K3/4682 ,  H05K2201/0376 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10674 ,  H05K2201/10977 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/0665

Abstract: The present invention provides a package structure with an embedded electronic component and a method of fabricating the package structure. The method includes: forming a first wiring layer on a carrier; removing the carrier and forming the first wiring layer on a bonding carrier; disposing an electronic component on the first wiring layer; forming an encapsulating layer, a second wiring layer and an insulating layer on the first wiring layer; disposing a chip on the electronic component and the second wiring layer; and forming a covering layer that covers the chip. The present invention can effectively reduce the thickness of the package structure and the electronic component without using adhesives.

Abstract translation: 本发明提供一种具有嵌入式电子部件的封装结构和制造封装结构的方法。 该方法包括：在载体上形成第一布线层; 移除载体并在键合载体上形成第一布线层; 在第一布线层上设置电子部件; 在所述第一布线层上形成封装层，第二布线层和绝缘层; 在所述电子部件和所述第二布线层上设置芯片; 并形成覆盖芯片的覆盖层。 本发明可以有效地减少包装结构和电子部件的厚度而不使用粘合剂。

公开(公告)号：US20150333029A1

公开(公告)日：2015-11-19

申请号：US14459713

申请日：2014-08-14

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yu-cheng Pai ,  Chun- Hsien Lin ,  Shih-Chao Chiu ,  Wei-Chung Hsiao ,  Ming-Chen Sun ,  Tzu-Chieh Shen ,  Chia-Cheng Chen

IPC: H01L23/00 ,  H01L23/48

CPC classification number: H01L21/486 ,  H01L21/4853 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/09 ,  H01L24/11 ,  H01L24/17 ,  H01L2224/02185 ,  H01L2224/0219 ,  H01L2924/0002

Abstract: A package substrate and a method of fabricating the same are provided. The method includes providing a substrate body having a first surface, a second surface opposing the first surface, a plurality of first electrical connecting pads disposed on the first surface; mounting a metal board on the first electrical connecting pads; and patterning the metal board so as to define a plurality of metal pillars corresponding to the first electrical connecting pads. Therefore, drawbacks of raw edges and unequal heights of the metal pillars can be obviated.

Abstract translation: 提供封装基板及其制造方法。 该方法包括提供具有第一表面，与第一表面相对的第二表面的衬底主体，设置在第一表面上的多个第一电连接焊盘; 将金属板安装在第一电连接垫上; 以及图案化所述金属板以限定对应于所述第一电连接焊盘的多个金属柱。 因此，可以消除金属柱的原始边缘和不等高度的缺点。

公开(公告)号：US20150303073A1

公开(公告)日：2015-10-22

申请号：US14755372

申请日：2015-06-30

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yu-Cheng Pai ,  Chun-Hsien Lin ,  Wei-Chung Hsiao ,  Ming-Chen Sun ,  Liang-Yi Hung

IPC: H01L21/48 ,  H01L23/498 ,  H01L21/683

CPC classification number: H01L21/4857 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: A method of fabricating a packaging substrate is provided, including: providing a carrier having two carrying portions, each of the carrying portions having a first side and a second side opposite to the first side and the carrying portions are bonded through the second sides thereof; forming a circuit layer on the first side of each of the carrying portions; and separating the two carrying portions from each other to form two packaging substrates. The carrying portions facilitate the thinning of the circuit layers and provide sufficient strength for the packaging substrates to undergo subsequent packaging processes. The carrying portions can be removed after the packaging processes to reduce the thickness of packages and thereby meet the miniaturization requirement.

Abstract translation: 提供了一种制造封装基板的方法，包括：提供具有两个承载部分的载体，每个承载部分具有第一侧和与第一侧相对的第二侧，并且承载部分通过其第二侧接合; 在每个所述承载部分的第一侧上形成电路层; 并将两个承载部分彼此分离以形成两个包装基板。 承载部分有助于电路层的薄化，并为包装基材提供足够的强度以经历后续包装过程。 可以在包装过程之后移除承载部分以减小包装的厚度，从而满足小型化要求。