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    Method of forming a wiring having carbon nanotube
    1.
    发明申请
    Method of forming a wiring having carbon nanotube 有权
    形成具有碳纳米管的布线的方法

    公开(公告)号：US20090271982A1

    公开(公告)日：2009-11-05

    申请号：US12387299

    申请日：2009-04-29

    申请人： Sun-Woo Lee ,  Seong-Ho Moon ,  Dong-Woo Kim ,  Jung-Hyeon Kim ,  Hong-Sik Yoon

    发明人： Sun-Woo Lee ,  Seong-Ho Moon ,  Dong-Woo Kim ,  Jung-Hyeon Kim ,  Hong-Sik Yoon

    IPC分类号： H05K3/10

    CPC分类号： H01L21/76879 ,  H01L21/76849 ,  H01L23/5252 ,  H01L23/53276 ,  H01L2221/1094 ,  H01L2924/0002 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49155 ,  H01L2924/00

    摘要： In a method of forming a wiring having a carbon nanotube, a lower wiring is formed on a substrate, and a catalyst layer is formed on the lower wiring. An insulating interlayer is formed on the substrate to cover the catalyst layer, and an opening is formed through the insulating interlayer to expose an upper face of the catalyst layer. A carbon nanotube wiring is formed in the opening, and an upper wiring is formed on the carbon nanotube wiring and the insulating interlayer to be electrically connected to the carbon nanotube wiring. A thermal stress is generated between the carbon nanotube wiring and the upper wiring to produce a dielectric breakdown of a native oxide layer formed on a surface of the carbon nanotube wiring. A wiring having a reduced electrical resistance between the carbon nanotube wiring and the upper wiring may be obtained.

    摘要翻译： 在形成具有碳纳米管的布线的方法中，在基板上形成下布线，并且在下布线上形成催化剂层。 在衬底上形成绝缘中间层以覆盖催化剂层，并且通过绝缘中间层形成开口以暴露催化剂层的上表面。 在开口部形成有碳纳米管布线，在碳纳米管布线和绝缘中间层上形成上部配线，与碳纳米管配线电连接。 在碳纳米管布线和上布线之间产生热应力，以产生形成在碳纳米管布线表面上的天然氧化物层的电介质击穿。 可以获得碳纳米管布线和上布线之间的电阻降低的布线。

    Method of forming a wiring having carbon nanotube
    2.
    发明授权
    Method of forming a wiring having carbon nanotube 有权
    形成具有碳纳米管的布线的方法

    公开(公告)号：US07877865B2

    公开(公告)日：2011-02-01

    申请号：US12387299

    申请日：2009-04-29

    申请人： Sun-Woo Lee ,  Seong-Ho Moon ,  Dong-Woo Kim ,  Jung-Hyeon Kim ,  Hong-Sik Yoon

    发明人： Sun-Woo Lee ,  Seong-Ho Moon ,  Dong-Woo Kim ,  Jung-Hyeon Kim ,  Hong-Sik Yoon

    IPC分类号： H01R43/00 ,  H01L21/44

    CPC分类号： H01L21/76879 ,  H01L21/76849 ,  H01L23/5252 ,  H01L23/53276 ,  H01L2221/1094 ,  H01L2924/0002 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49155 ,  H01L2924/00

    摘要： In a method of forming a wiring having a carbon nanotube, a lower wiring is formed on a substrate, and a catalyst layer is formed on the lower wiring. An insulating interlayer is formed on the substrate to cover the catalyst layer, and an opening is formed through the insulating interlayer to expose an upper face of the catalyst layer. A carbon nanotube wiring is formed in the opening, and an upper wiring is formed on the carbon nanotube wiring and the insulating interlayer to be electrically connected to the carbon nanotube wiring. A thermal stress is generated between the carbon nanotube wiring and the upper wiring to produce a dielectric breakdown of a native oxide layer formed on a surface of the carbon nanotube wiring. A wiring having a reduced electrical resistance between the carbon nanotube wiring and the upper wiring may be obtained.

    摘要翻译： 在形成具有碳纳米管的布线的方法中，在基板上形成下布线，并且在下布线上形成催化剂层。 在衬底上形成绝缘中间层以覆盖催化剂层，并且通过绝缘中间层形成开口以暴露催化剂层的上表面。 在开口部形成有碳纳米管布线，在碳纳米管布线和绝缘中间层上形成上部配线，与碳纳米管配线电连接。 在碳纳米管布线和上布线之间产生热应力，以产生形成在碳纳米管布线表面上的天然氧化物层的电介质击穿。 可以获得碳纳米管布线和上布线之间的电阻降低的布线。

    Methods of forming a phase change memory device
    5.
    发明授权
    Methods of forming a phase change memory device 有权
    形成相变存储器件的方法

    公开(公告)号：US08187914B2

    公开(公告)日：2012-05-29

    申请号：US12731637

    申请日：2010-03-25

    申请人： Jin-Il Lee ,  Urazaev Vladimir ,  Jin-Ha Jeong ,  Seung-Back Shin ,  Sung-Lae Cho ,  Hyeong-Geun An ,  Dong-Hyun Im ,  Young-Lim Park ,  Jung-Hyeon Kim

    发明人： Jin-Il Lee ,  Urazaev Vladimir ,  Jin-Ha Jeong ,  Seung-Back Shin ,  Sung-Lae Cho ,  Hyeong-Geun An ,  Dong-Hyun Im ,  Young-Lim Park ,  Jung-Hyeon Kim

    IPC分类号： H01L21/20

    CPC分类号： H01L45/1616 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1683

    摘要： Provided are methods of forming a phase change memory device. A semiconductor device having a lower electrode and an interlayer insulating layer may be prepared. The lower electrode may be surrounded by the interlayer insulating layer. Source gases, a reaction gas and a purge gas may be injected into a process chamber of a semiconductor fabrication device to form a phase change material layer on a semiconductor substrate. The source gases may be simultaneously injected into the process chamber. The phase change material layer may be in contact with the lower electrode through the interlayer insulating layer. The phase change material layer may be etched to form a phase change memory cell in the interlayer insulating layer. An upper electrode may be formed on the phase change memory cell.

    摘要翻译： 提供形成相变存储器件的方法。 可以制备具有下电极和层间绝缘层的半导体器件。 下电极可以被层间绝缘层包围。 可以将源气体，反应气体和吹扫气体注入到半导体制造装置的处理室中，以在半导体衬底上形成相变材料层。 源气体可以同时注入到处理室中。 相变材料层可以通过层间绝缘层与下电极接触。 可以蚀刻相变材料层以在层间绝缘层中形成相变存储单元。 可以在相变存储单元上形成上电极。

    Semiconductor memory device
    6.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US08130577B2

    公开(公告)日：2012-03-06

    申请号：US12590417

    申请日：2009-11-06

    申请人： Jong-Hak Won ,  Young-Soo An ,  Jung-Hyeon Kim

    发明人： Jong-Hak Won ,  Young-Soo An ,  Jung-Hyeon Kim

    IPC分类号： G11C8/00

    CPC分类号： G11C7/08 ,  G11C5/025 ,  G11C7/1012 ,  G11C7/12 ,  G11C2207/002

    摘要： A semiconductor memory device includes a sub memory cell array region having memory cells each connected between word lines extending in a first direction and bit lines extending in a second direction that is orthogonal to the first direction of extension of the word lines and a sub word line driver region disposed at a side of the sub memory cell array region in the first direction and including sub word line drivers that activate the word lines. A sensing region is disposed at a side of the sub memory cell array region in the second direction and including an equalizer that precharges the bit line in response to a signal transferred through a drive signal line and at least one first control signal driver that activates an inverted control signal line in response to a signal transferred through a control signal line. A conjunction region disposed at an intersection between the sub word line driver region and the sensing region, in which the inverted control signal line is connected to the drive signal line.

    摘要翻译： 半导体存储器件包括具有存储单元的子存储单元阵列区域，每个存储单元分别连接在沿第一方向延伸的字线和沿着与字线的第一延伸方向正交的第二方向延伸的位线和一个子字线 驱动器区域，设置在副存储单元阵列区域的第一方向的一侧，并且包括激活字线的子字线驱动器。 感测区域设置在副存储单元阵列区域的第二方向的一侧，并且包括响应于通过驱动信号线传送的信号而对位线进行预充电的均衡器，以及至少一个第一控制信号驱动器，其激活 响应于通过控制信号线传送的信号的反相控制信号线。 配置在副字线驱动器区域和感测区域之间的交叉点处的连接区域，其中反相控制信号线连接到驱动信号线。

    Semiconductor device and method of manufacturing the same
    7.
    发明授权
    Semiconductor device and method of manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US07906423B2

    公开(公告)日：2011-03-15

    申请号：US12650093

    申请日：2009-12-30

    申请人： Hyo-Jae Bang ,  Heui-Seog Kim ,  Dong-Chun Lee ,  Seong-Chan Han ,  Jung-Hyeon Kim

    发明人： Hyo-Jae Bang ,  Heui-Seog Kim ,  Dong-Chun Lee ,  Seong-Chan Han ,  Jung-Hyeon Kim

    IPC分类号： H01L21/44

    CPC分类号： H05K3/303 ,  H05K2201/0305 ,  H05K2201/09781 ,  H05K2201/10689 ,  H05K2201/2036 ,  Y02P70/613

    摘要： A semiconductor device includes a semiconductor package, a circuit board and an interval maintaining member. The semiconductor package has a body and a lead protruded from the body. The circuit board has a first land electrically connected to the lead. The interval maintaining member is interposed between the circuit board and the body. The interval maintaining member maintains an interval between the lead and the first land. Thus, an interval between the lead and the land is uniformly maintained, so that a thermal and/or mechanical reliability of the semiconductor device is improved.

    摘要翻译： 半导体器件包括半导体封装，电路板和间隔保持元件。 半导体封装具有从主体突出的主体和引线。 电路板具有与引线电连接的第一焊盘。 间隔保持构件插入在电路板和主体之间。 间隔保持构件保持引线与第一焊盘之间的间隔。 因此，均匀地保持引线和焊盘之间的间隔，从而提高了半导体器件的热和/或机械可靠性。