公开(公告)号：US20240168084A1

公开(公告)日：2024-05-23

申请号：US18085560

申请日：2022-12-20

Applicant: United Microelectronics Corp.

Inventor： Jih-Shun Chiang ,  Wen-Chun Chang ,  Wen-Hsiung Ko ,  Sung-Nien Kuo ,  Kuan-Cheng Su

IPC: G01R31/28 ,  H01L23/34 ,  H01L23/528 ,  H01L23/532

CPC classification number: G01R31/2875 ,  H01L23/345 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/5329

Abstract: A semiconductor structure is provided. The semiconductor structure includes at least one metal gate structure and a device to be tested. The metal gate structure is disposed on a substrate. The device to be tested is disposed on the metal gate structure and electrically separated from the metal gate structure. The device to be tested is heated by a heat generated when the metal gate structure is applied with a voltage.

公开(公告)号：US11189611B2

公开(公告)日：2021-11-30

申请号：US16844986

申请日：2020-04-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Yu Huang ,  Kuan-Cheng Su ,  Tien-Hao Tang ,  Ping-Jui Chen ,  Po-Ya Lai

IPC: H01L27/02 ,  H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/10

Abstract: An ESD protection semiconductor device includes a substrate. A gate set disposed on the substrate. A plurality of source fins and a plurality of drain fins having a first conductivity type are disposed in the substrate respectively at two sides of the gate set. A first doped fin is disposed in the substrate and positioned in between the source fins and spaced apart from the source fins. The first doped fin comprises a second conductivity type that is complementary to the first conductivity type. A second doped fin is formed in one of the drain fins and isolated from the one of the drain fins by an isolation structure. The second doped fin is electrically connected to the first doped fin.

公开(公告)号：US20180158902A1

公开(公告)日：2018-06-07

申请号：US15402204

申请日：2017-01-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hou-Jen Chiu ,  Ya-Ting Lin ,  Mei-Ling Chao ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L29/06 ,  H01L29/78

CPC classification number: H01L29/0638 ,  H01L29/0653 ,  H01L29/7851

Abstract: A semiconductor device comprises a fin shaped structure, a shallow trench isolation, a diffusion break structure and a gate electrode. The fin shaped structure is disposed on a substrate. The shallow trench isolation is disposed in the substrate and surrounds the fin shaped structure. The diffusion break structure is disposed in the fin shaped structure, and the gate electrode is disposed across the fin shaped structure.

公开(公告)号：US09653450B2

公开(公告)日：2017-05-16

申请号：US14938850

申请日：2015-11-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Yu Huang ,  Kuan-Cheng Su ,  Tien-Hao Tang ,  Ping-Jui Chen ,  Po-Ya Lai

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/0255 ,  H01L27/0207 ,  H01L27/027 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1087 ,  H01L29/7819 ,  H01L29/7831 ,  H01L29/7835 ,  H01L29/785 ,  H01L29/7851

Abstract: An ESD protection semiconductor device includes a substrate, a gate set formed on the substrate, a source region and a drain region formed in the substrate respectively at two sides of the gate set, and at least a first doped region formed in the drain region. The source region and the drain region include a first conductivity type, and the first doped region includes a second conductivity type. The first conductivity type and the second conductivity type are complementary to each other. The first doped region is electrically connected to a ground potential.

公开(公告)号：US09368484B1

公开(公告)日：2016-06-14

申请号：US14723482

申请日：2015-05-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Chun Chen ,  Ping-Chen Chang ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L27/02 ,  H01L27/088 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L27/0266 ,  H01L27/0248 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/41791 ,  H01L29/7851

Abstract: A fin type ESD protection device includes at least one first fin, at least one second fin, and at least one gate structure. The first fin is disposed on a semiconductor substrate, and a source contact contacts the first fin. The second fin is disposed on the semiconductor substrate, and a drain contact contacts the second fin. The first fin and the second fin extend in a first direction respectively, and the first fin is separated from the second fin. The gate structure is disposed between the source contact and the drain contact. The first fin is separated from the drain contact, and the second fin is separated from the source contact.

Abstract translation: 翅片型ESD保护装置包括至少一个第一鳍片，至少一个第二鳍片和至少一个栅极结构。 第一翅片设置在半导体衬底上，源极触点接触第一鳍片。 第二鳍片设置在半导体衬底上，漏极接触件接触第二鳍片。 第一鳍片和第二鳍片分别在第一方向上延伸，并且第一鳍片与第二鳍片分离。 栅极结构设置在源极触点和漏极触点之间。 第一鳍片与漏极接触部分开，第二鳍片与源极接触部分离开。

公开(公告)号：US20160126331A1

公开(公告)日：2016-05-05

申请号：US14554068

申请日：2014-11-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chi-Ju Lee ,  Yao-Chang Wang ,  Nien-Ting Ho ,  Chi-Mao Hsu ,  Kuan-Cheng Su ,  Main-Gwo Chen ,  Hsiao-Kwang Yang ,  Fang-Hong Yao ,  Sheng-Huei Dai ,  Tzung-Lin Li

IPC: H01L29/423 ,  H01L21/02 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/42376 ,  H01L21/02178 ,  H01L21/02186 ,  H01L21/02194 ,  H01L21/02244 ,  H01L21/02255 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/78

Abstract: The present invention provides a metal gate structure which is formed in a trench of a dielectric layer. The metal gate structure includes a work function metal layer and a metal layer. The work function metal layer is disposed in the trench and comprises a bottom portion and a side portion, wherein a ratio between a thickness of the bottom portion and a thickness of the side portion is between 2 and 5. The trench is filled with the metal layer. The present invention further provides a method of forming the metal gate structure.

Abstract translation: 本发明提供了形成在电介质层的沟槽中的金属栅极结构。 金属栅极结构包括功函数金属层和金属层。 工作功能金属层设置在沟槽中，并且包括底部和侧部，其中底部的厚度和侧部的厚度之间的比率在2-5之间。沟槽填充有金属 层。 本发明还提供一种形成金属栅极结构的方法。

公开(公告)号：US20150287838A1

公开(公告)日：2015-10-08

申请号：US14742723

申请日：2015-06-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Tzu Wang ,  Ping-Chen Chang ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L29/861 ,  H01L29/06

CPC classification number: H01L27/0255 ,  H01L21/22 ,  H01L21/265 ,  H01L21/30604 ,  H01L21/76 ,  H01L21/76224 ,  H01L27/0629 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/1606 ,  H01L29/2003 ,  H01L29/6609 ,  H01L29/66136 ,  H01L29/785 ,  H01L29/861

Abstract: A fin diode structure includes a doped well formed in a substrate, a plurality of fins of first conductivity type and a plurality of fins of second conductivity type protruding from the doped well isolated from ins of first conductivity type by STIs, at least one doped region of first conductivity type in the substrate between the fins of first conductivity type, the STIs and the doped well and connecting with the fins of first conductivity type, and at least one doped region of second conductivity type in the substrate between the fins of second conductivity type, the STIs and the doped well and connecting with the fins of second conductivity type. The doping concentration of the fins of first conductivity type is greater than that of the doped region of first conductivity type whose doping concentration is greater than that of the doped well of first conductivity type.

Abstract translation: 翅片二极管结构包括在衬底中形成的掺杂阱，第一导电类型的多个鳍和第二导电类型的多个翅片，其通过STI从与第一导电类型的绝缘体隔离的掺杂阱突出，至少一个掺杂区域 第一导电类型的翅片之间的衬底中的第一导电类型，STI和掺杂阱并且与第一导电类型的鳍连接并且在第二导电类型的鳍之间的衬底中的至少一个第二导电类型的掺杂区域 类型，STI和掺杂阱，并与第二导电类型的鳍连接。 第一导电类型的散热片的掺杂浓度大于其掺杂浓度大于第一导电类型的掺杂阱的第一导电类型的掺杂区域的掺杂浓度。

公开(公告)号：US20150123184A1

公开(公告)日：2015-05-07

申请号：US14071670

申请日：2013-11-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Tzu Wang ,  Yu-Chun Chen ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L27/092 ,  H01L27/06 ,  H01L23/60 ,  H01L29/78

CPC classification number: H01L27/0925 ,  H01L21/823892 ,  H01L27/0274 ,  H01L27/0629 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/785

Abstract: A CMOS device includes a substrate, a pMOS transistor and an nMOS transistor formed on the substrate, and a gated diode. The gated diode includes a floating gate formed on the substrate in between the pMOS transistor and the nMOS transistor and a pair of a p-doped region and an n-doped region formed in the substrate and between the pMOS transistor and the nMOS transistor. The n-doped region is formed between the floating gate and the nMOS transistor, and the p-doped region is formed between the floating gate and the pMOS transistor.

Abstract translation: CMOS器件包括衬底，pMOS晶体管和形成在衬底上的nMOS晶体管，以及门控二极管。 门控二极管包括形成在pMOS晶体管和nMOS晶体管之间的衬底上的浮置栅极和形成在衬底中以及在pMOS晶体管和nMOS晶体管之间的一对p掺杂区域和n掺杂区域。 在浮置栅极和nMOS晶体管之间形成n掺杂区域，并且在浮置栅极和pMOS晶体管之间形成p掺杂区域。

公开(公告)号：US20230299158A1

公开(公告)日：2023-09-21

申请号：US17719351

申请日：2022-04-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuan-Yu Lu ,  Hou-Jen Chiu ,  Mei-Ling Chao ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L29/417 ,  H01L23/522 ,  H01L27/02

CPC classification number: H01L29/41775 ,  H01L23/5226 ,  H01L27/0266 ,  H01L29/7835

Abstract: An electrostatic discharge (ESD) protection device includes a semiconductor substrate, a gate structure, a source doped region, a drain doped region, source silicide patterns, and drain silicide patterns. The gate structure is disposed on the semiconductor substrate. The source doped region and the drain doped region are disposed in the semiconductor substrate and located at two opposite sides of the gate structure in a first direction, respectively. The source silicide patterns are disposed on the source doped region. The source silicide patterns are arranged in a second direction and separated from one another. The drain silicide patterns are disposed on the drain doped region. The drain silicide patterns are arranged in the second direction and separated from one another. The source silicide patterns and the drain silicide patterns are arranged misaligned with one another in the first direction.

公开(公告)号：US20180254268A1

公开(公告)日：2018-09-06

申请号：US15445999

申请日：2017-03-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Che Yen ,  Po-Ya Lai ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L27/02 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L29/749 ,  H01L29/66

CPC classification number: H01L27/027 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/66356 ,  H01L29/749

Abstract: An ESD protection device includes a semiconductor substrate, a well, a gate structure, a first source/drain region, a second source/drain region, a first doped region, and a second doped region. The well is disposed in the semiconductor substrate. The gate structure is disposed on the well. The first source/drain region and the second source/drain region are disposed in the well and disposed at two opposite sides of the gate structure respectively. The first doped region is disposed in the first source/drain region. The second doped region is disposed in the second source/drain region. A conductivity type of the first doped region is complementary to that of the first source/drain region. A conductivity type of the second doped region is complementary to that of the second source/drain region. A conductivity type of the well is complementary to that of the first source/drain region and the second source/drain region.