公开(公告)号：US20130154077A1

公开(公告)日：2013-06-20

申请号：US13720649

申请日：2012-12-19

Applicant: Xintec Inc.

Inventor： Kuo-Hua LIU ,  Yi-Ming CHANG ,  Hsi-Chien LIN

IPC: H01L21/78 ,  H01L23/48

CPC classification number: H01L21/78 ,  H01L21/50 ,  H01L21/561 ,  H01L23/10 ,  H01L23/48 ,  H01L27/14618 ,  H01L27/14632 ,  H01L27/14687 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A chip package includes: a substrate having a first and a second surfaces; a device region formed in or disposed on the substrate; a dielectric layer disposed on the first surface; at least one conducting pad disposed in the dielectric layer and electrically connected to the device region; a planar layer disposed on the dielectric layer, wherein a vertical distance between upper surfaces of the planar layer and the conducting pad is larger than about 2 μm; a transparent substrate disposed on the first surface; a first spacer layer disposed between the transparent substrate and the planar layer; and a second spacer layer disposed between the transparent substrate and the substrate and extending into an opening of the dielectric layer to contact with the conducting pad, wherein there is substantially no gap between the second spacer layer and the conducting pad.

Abstract translation: 芯片封装包括：具有第一和第二表面的衬底; 形成在基板上或设置在基板上的器件区域; 设置在所述第一表面上的电介质层; 至少一个导电焊盘，其布置在所述电介质层中并电连接到所述器件区域; 设置在所述电介质层上的平面层，其中所述平面层的上表面与所述导电焊盘之间的垂直距离大于约2μm; 设置在所述第一表面上的透明基板; 设置在所述透明基板和所述平面层之间的第一间隔层; 以及第二间隔层，其设置在所述透明基板和所述基板之间并且延伸到所述电介质层的与所述导电焊盘接触的开口中，其中所述第二间隔层和所述导电焊盘之间基本上没有间隙。

公开(公告)号：US20170207194A1

公开(公告)日：2017-07-20

申请号：US15409511

申请日：2017-01-18

Applicant: XINTEC INC.

Inventor： Hsing-Lung SHEN ,  Jiun-Yen LAI ,  Yu-Ting HUANG ,  Tsung-Cheng CHAN ,  Jan-Lian LIAO ,  Hung-Chang CHEN ,  Ming-Chieh HUANG ,  Hsi-Chien LIN

IPC: H01L25/065 ,  H01L23/29 ,  H01L21/56 ,  H01L25/00 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L24/03 ,  H01L21/563 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3171 ,  H01L23/3178 ,  H01L24/06 ,  H01L24/13 ,  H01L24/24 ,  H01L24/82 ,  H01L24/94 ,  H01L25/50 ,  H01L2224/02373 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/24145 ,  H01L2224/82005 ,  H01L2224/94 ,  H01L2924/10253 ,  H01L2924/1433 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2224/82

Abstract: A chip package is provided. The chip package includes a first chip including a carrier substrate and a device substrate thereon. A second chip is mounted on the device substrate. A portion of the device substrate extends outward from the edge of the second chip, so as to be exposed from the second chip. A conductive pad is between the device substrate and the second chip. A polymer protective layer conformally covers the second chip, the exposed portion of the device substrate, and the edge of the carrier substrate. A redistribution layer is disposed on the polymer protective layer and extends into a first opening that passes through the polymer protective layer and the second chip and exposes the conductive pad, so as to be electrically connected to the conductive pad.

公开(公告)号：US20170186797A1

公开(公告)日：2017-06-29

申请号：US15393006

申请日：2016-12-28

Applicant: XINTEC INC.

Inventor： Shun-Wen LONG ,  Guo-Jyun CHIOU ,  Meng-Han KUO ,  Ming-Chieh HUANG ,  Hsi-Chien LIN ,  Chin-Kang CHEN ,  Yi-Pin CHEN

IPC: H01L27/146

CPC classification number: H01L27/14629 ,  H01L27/14623 ,  H01L27/14636 ,  H01L27/14685 ,  H01L27/14698 ,  H01L2224/11

Abstract: A chip package includes a chip, an insulating layer and a conductive layer. The chip includes a substrate, an epitaxy layer, a device region and a conductive pad. The epitaxy layer is disposed on the substrate, and the device region and the conductive pad are disposed on the epitaxy layer. The conductive pad is at a side of the device region and connected to the device region. The conductive pad protrudes out of a side surface of the epitaxy layer. The insulating layer is disposed below the substrate and extended to cover the side surface of the epitaxy layer. The conductive layer is disposed below the insulating layer and extended to contact the conductive pad. The conductive layer and the side surface of the epitaxy layer are separated by a first distance.

公开(公告)号：US20160343882A1

公开(公告)日：2016-11-24

申请号：US15157776

申请日：2016-05-18

Applicant: XINTEC INC.

Inventor： Yi-Ying KUO ,  Ming-Chieh HUANG ,  Hsi-Chien LIN

IPC: H01L31/02 ,  H01L31/18 ,  H01L31/0216

CPC classification number: H01L31/02002 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/562 ,  H01L31/0216 ,  H01L31/186 ,  H01L2224/11

Abstract: A chip package includes a chip, an insulating layer, a flowing insulating material layer and conductive layer. The chip has a conductive pad, a side surface, a first surface and a second surface opposite to the first surface, which the side surface is between the first surface and the second surface, and the conductive is below the first surface and protruded from the side surface. The insulating layer covers the second surface and the side surface, and the flowing insulating material layer is disposed below the insulating layer, and the flowing insulating material layer has a trench exposing the conductive pad protruded form the side surface. The conductive layer is disposed below the flowing insulating material layer and extended into the trench to contact the conductive pad.

Abstract translation: 芯片封装包括芯片，绝缘层，流动绝缘材料层和导电层。 芯片具有导电焊盘，侧表面，与第一表面相对的第一表面和第二表面，侧表面位于第一表面和第二表面之间，并且导电体在第一表面下方并且从第一表面突出 侧面。 绝缘层覆盖第二表面和侧表面，并且流动绝缘材料层设置在绝缘层下方，并且流动绝缘材料层具有暴露从侧表面突出的导电焊盘的沟槽。 导电层设置在流动的绝缘材料层下方并延伸到沟槽中以接触导电焊盘。

公开(公告)号：US20180012853A1

公开(公告)日：2018-01-11

申请号：US15643012

申请日：2017-07-06

Applicant: XINTEC INC.

Inventor： Hsi-Chien LIN ,  Jyh-Wei CHEN ,  Jun-Chi HSIEH ,  Yue-Ting CHEN

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  G06K9/00

CPC classification number: H01L24/02 ,  G06K9/00013 ,  H01L21/56 ,  H01L23/3114 ,  H01L23/3142 ,  H01L23/3171 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/82 ,  H01L24/94 ,  H01L24/96 ,  H01L27/14618 ,  H01L27/1462 ,  H01L27/14685 ,  H01L2224/02333 ,  H01L2224/0235 ,  H01L2224/0236 ,  H01L2224/0237 ,  H01L2224/02371 ,  H01L2224/02373 ,  H01L2224/02381 ,  H01L2224/03019 ,  H01L2224/04105 ,  H01L2224/08221 ,  H01L2224/11002 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/73259 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2924/10155 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/0231 ,  H01L2224/11 ,  H01L2224/19

Abstract: A chip package includes a chip, an isolation layer on the bottom surface and the sidewall, a redistribution layer that is on the isolation layer and in electrical contact with a side surface of the conductive pad, and a passivation layer. The chip has a sensor, at least one conductive pad, a top surface, a bottom surface, and a sidewall. The sensor is located on the top surface. The conductive pad is located on an edge of the top surface. The redistribution layer at least partially protrudes from the conductive pad so as to be exposed. The passivation layer is located on the isolation layer and the redistribution layer, such that the redistribution layer not protruding from the conductive pad is between the passivation layer and the isolation layer, and the redistribution layer protruding from the conductive pad is located on the passivation layer.

公开(公告)号：US20170088417A1

公开(公告)日：2017-03-30

申请号：US15275693

申请日：2016-09-26

Applicant: XINTEC INC.

Inventor： Yu-Chen LAI ,  Meng-Han KUO ,  Ming-Chieh HUANG ,  Hsi-Chien LIN

IPC: B81C1/00 ,  B81B7/00 ,  H01L27/146

CPC classification number: H01L27/146 ,  B81B7/02 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81C1/00238 ,  B81C2203/0792

Abstract: An electronic device includes an image sensor that has a device layer and a MEMS device that is located on the image sensor and includes a MEMS element, a cap element, and a cover layer. The MEMS element having plural hollow regions is located on the device layer, such that a first cavity is formed between the MEMS element and the image sensor. The cap element having an opening is located on a surface of the MEMS element facing away from the device layer, such that a second cavity is formed between the cap element and the MEMS element and communicates with the opening. The first cavity communicates with the second cavity through the hollow regions. The cover layer is located on a surface of the cap element facing away from the MEMS element and is located in the opening of the cap element.

公开(公告)号：US20170025370A1

公开(公告)日：2017-01-26

申请号：US15209723

申请日：2016-07-13

Applicant: XINTEC INC.

Inventor： Yin-Chen CHEN ,  Jan-Lian LIAO ,  Ming-Chieh HUANG ,  Jyh-Wei CHEN ,  Hsi-Chien LIN

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/31 ,  H01L21/683 ,  H01L21/78

CPC classification number: H01L24/06 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/3171 ,  H01L24/00 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/29 ,  H01L24/43 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0231 ,  H01L2224/0233 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/0605 ,  H01L2924/00014 ,  H01L2224/45099

Abstract: This present invention provides a method of manufacturing a chip scale sensing chip package, comprising the steps of: providing a sensing device wafer having a first top surface and a first bottom surface opposite to each other, whereby the sensing device wafer comprises a plurality of chip areas, and each of the chip areas comprising a sensing device and a plurality of conductive pads adjacent to the sensing chip nearby the first top surface; providing a cap wafer having a second top surface and a second bottom surface opposite to each other, and bonding the second surface of the cap wafer to the first top surface of the sensing device wafer by sandwiching a first adhesive layer therebetween; providing a temporary carrier substrate, and bonding the temporary carrier substrate to the second top surface of the cap wafer by sandwiching a second adhesive layer therebetween; forming a wiring layer connecting to each of the conductive pads on the first bottom surface of the sensing device wafer; providing a first protective layer on the wiring layer; removing the temporary carrier substrate and the second adhesive layer; forming a second protective layer on the second top surface; removing the first protective layer; scribing the chip areas to generate a plurality of individual chip scale sensing chip package; and removing the second protective layer.

Abstract translation: 本发明提供了一种制造芯片级感测芯片封装的方法，包括以下步骤：提供具有彼此相对的第一顶表面和第一底表面的感测装置晶片，由此感测装置晶片包括多个芯片 区域，并且每个芯片区域包括感测装置和与第一顶表面附近的感测芯片相邻的多个导电焊盘; 提供具有彼此相对的第二顶表面和第二底表面的盖晶片，并且通过在其间夹住第一粘合剂层将盖晶片的第二表面粘合到感测装置晶片的第一顶表面; 提供临时载体基板，并且通过在其间夹着第二粘合剂层将临时载体基板结合到盖晶片的第二顶表面; 形成连接到感测装置晶片的第一底表面上的每个导电焊盘的布线层; 在所述布线层上提供第一保护层; 去除所述临时载体基板和所述第二粘合剂层; 在所述第二顶表面上形成第二保护层; 去除第一保护层; 划片芯片区域以产生多个单独的芯片级感测芯片封装; 并移除第二保护层。