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    CHIP PACKAGE AND METHOD FOR FORMING THE SAME
    1.
    发明申请
    CHIP PACKAGE AND METHOD FOR FORMING THE SAME 有权
    芯片包装及其形成方法

    公开(公告)号：US20130320559A1

    公开(公告)日：2013-12-05

    申请号：US13900081

    申请日：2013-05-22

    Applicant: XINTEC INC.

    Inventor： Yu-Ting HUANG ,  Shu-Ming CHANG ,  Yen-Shih HO ,  Tsang-Yu LIU

    IPC: B81B7/00

    CPC classification number: B81B7/0077 ,  B81B7/007 ,  B81B2207/095 ,  B81B2207/096 ,  H01L21/64 ,  H01L23/481 ,  H01L23/498 ,  H01L23/525 ,  H01L24/02 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2224/02311 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/06182 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/014 ,  H01L2924/00

    Abstract: An embodiment of the invention provides a chip package including: a first semiconductor substrate; a second semiconductor substrate disposed on the first semiconductor substrate, wherein the second semiconductor substrate includes a lower semiconductor layer, an upper semiconductor layer, and an insulating layer located between the lower semiconductor layer and the upper semiconductor layer, and a portion of the lower semiconductor layer electrically contacts with at least a pad on the first semiconductor substrate; a signal conducting structure disposed on a lower surface of the first semiconductor substrate, wherein the signal conducting structure is electrically connected to a signal pad on the first semiconductor substrate; and a conducting layer disposed on the upper semiconductor layer of the second semiconductor substrate and electrically contacted with the portion of the lower semiconductor layer electrically contacting with the at least one pad on the first semiconductor substrate.

    Abstract translation: 本发明的实施例提供一种芯片封装，包括：第一半导体衬底; 设置在所述第一半导体衬底上的第二半导体衬底，其中所述第二半导体衬底包括下半导体层，上半导体层和位于所述下半导体层和所述上半导体层之间的绝缘层，以及所述下半导体 层与第一半导体衬底上的至少焊盘电接触; 信号导通结构，设置在所述第一半导体衬底的下表面上，其中所述信号导电结构电连接到所述第一半导体衬底上的信号焊盘; 以及导电层，其设置在所述第二半导体衬底的所述上半导体层上并与所述下半导体层的与所述第一半导体衬底上的所述至少一个焊盘电接触的部分电接触。

    OPTICAL CHIP PACKAGE AND METHOD FOR FORMING THE SAME
    5.
    发明申请
    OPTICAL CHIP PACKAGE AND METHOD FOR FORMING THE SAME 审中-公开

    公开(公告)号：US20200333542A1

    公开(公告)日：2020-10-22

    申请号：US16851099

    申请日：2020-04-17

    Applicant: XINTEC INC.

    Inventor： Jiun-Yen LAI ,  Yu-Ting HUANG ,  Hsing-Lung SHEN ,  Tsang-Yu LIU ,  Hui-Hsien WU

    IPC: G02B6/42

    Abstract: An optical chip package is provided. The optical chip package includes a first transparent substrate, a second transparent substrate, and a spacer layer. The first and second transparent substrates each has a first surface and a second surface opposite the first surface. The first transparent substrate has a thickness that is different than that of the second transparent substrate. The second transparent substrate is disposed over the first transparent substrate, and the spacer layer is bonded between the second surface of the first transparent substrate and the first surface of the second transparent substrate. The recess region extends from the second surface of the second transparent substrate into the first transparent substrate, so that the first transparent substrate has a step-shaped sidewall. A method of forming an optical chip package is also provided.

    CHIP PACKAGE AND METHOD THEREOF
    6.
    发明申请
    CHIP PACKAGE AND METHOD THEREOF 有权
    芯片包装及其方法

    公开(公告)号：US20160039662A1

    公开(公告)日：2016-02-11

    申请号：US14747507

    申请日：2015-06-23

    Applicant: XINTEC INC.

    Inventor： Chien-Min LIN ,  Yu-Ting HUANG ,  Chen-Ning FU ,  Yen-Shih HO

    IPC: B81B7/00 ,  H01L21/48 ,  H01L23/498 ,  B81C1/00

    CPC classification number: B81B7/007 ,  B81C1/00182 ,  B81C1/00269 ,  B81C2201/0197 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A chip package includes a semiconductor chip, an interposer, a polymer adhesive supporting layer, a redistribution layer and a packaging layer. The semiconductor chip has a sensor device and a conductive pad electrically connected to the sensing device, and the interposer is disposed on the semiconductor chip. The interposer has a trench and a through hole, which the trench exposes a portion of the sensing device, and the through hole exposes the conductive pad. The polymer adhesive supporting layer is interposed between the semiconductor chip and the interposer, and the redistribution layer is disposed on the interposer and in the through hole to be electrically connected to the conductive pad. The packaging layer covers the interposer and the redistribution layer, which the packaging layer has an opening exposing the trench.

    Abstract translation: 芯片封装包括半导体芯片，插入件，聚合物粘合剂支撑层，再分布层和包装层。 半导体芯片具有传感器装置和与感测装置电连接的导电焊盘，并且插入器设置在半导体芯片上。 插入器具有沟槽和通孔，沟槽暴露感测装置的一部分，并且通孔暴露导电垫。 聚合物粘合剂支撑层插入在半导体芯片和插入件之间，并且再分配层设置在插入件上和通孔中以与导电焊盘电连接。 包装层覆盖插入件和再分配层，其中封装层具有露出沟槽的开口。

    CHIP PACKAGE AND METHOD FOR FORMING THE SAME
    7.
    发明申请
    CHIP PACKAGE AND METHOD FOR FORMING THE SAME 有权

    公开(公告)号：US20210210538A1

    公开(公告)日：2021-07-08

    申请号：US17133636

    申请日：2020-12-24

    Applicant: XINTEC INC.

    Inventor： Jiun-Yen LAI ,  Wei-Luen SUEN ,  Hsing-Lung SHEN ,  Yu-Ting HUANG

    IPC: H01L27/146

    Abstract: A chip package is provided. The chip package includes a first substrate and a second substrate disposed over the first substrate. The first substrate and the second substrate have a lower surface and an upper surface, and the second substrate includes a first recess region surrounding the second substrate. The first recess region has a tapered sidewall and a bottom surface that is between the lower and upper surfaces of the second substrate. The chip package also includes at least one conductive pad disposed on the upper surface of the second substrate and a redistribution layer (RDL) correspondingly disposed on the conductive pad. The RDL is extended from the conductive pad onto the bottom surface of the first recess region along the tapered sidewall of the first recess region. A method of forming a chip package is also provided.

    CHIP PACKAGE AND METHOD FOR FORMING THE SAME
    9.
    发明申请
    CHIP PACKAGE AND METHOD FOR FORMING THE SAME 有权
    芯片包装及其形成方法

    公开(公告)号：US20140084458A1

    公开(公告)日：2014-03-27

    申请号：US14036954

    申请日：2013-09-25

    Applicant: XINTEC INC.

    Inventor： Yu-Ting HUANG ,  Tsang-Yu LIU

    IPC: H01L23/498 ,  H01L21/768

    CPC classification number: H01L23/49827 ,  B81B7/0061 ,  H01L21/76885 ,  H01L23/3107 ,  H01L23/481 ,  H01L2224/13 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/00

    Abstract: An embodiment of the invention provides a chip package which includes: a substrate having a first surface and a second surface; a sensing layer disposed on the first surface of the substrate, wherein the sensing layer has a sensing region; a conducting pad structure disposed on the substrate and electrically connected to the sensing region; a spacer layer disposed on the first surface of the substrate; a semiconductor substrate placed on the spacer layer, wherein the semiconductor substrate, the spacer layer, and the substrate together surround a cavity on the sensing region; and a through-hole extending from a surface of the semiconductor substrate toward the substrate, wherein the through-hole connects to the cavity.

    Abstract translation: 本发明的实施例提供了一种芯片封装，其包括：具有第一表面和第二表面的基板; 感测层，其设置在所述基板的所述第一表面上，其中所述感测层具有感测区域; 导电焊盘结构，设置在所述基板上并电连接到所述感测区域; 设置在所述基板的第一表面上的间隔层; 放置在间隔层上的半导体衬底，其中半导体衬底，间隔层和衬底一起围绕感测区域上的空腔; 以及从半导体衬底的表面朝向衬底延伸的通孔，其中所述通孔连接到所述腔。

    CHIP PACKAGE AND METHOD FOR FORMING THE SAME
    10.
    发明申请
    CHIP PACKAGE AND METHOD FOR FORMING THE SAME 有权
    芯片包装及其形成方法

    公开(公告)号：US20130252368A1

    公开(公告)日：2013-09-26

    申请号：US13893015

    申请日：2013-05-13

    Applicant: XINTEC INC.

    Inventor： Yu-Lung HUANG ,  Yu-Ting HUANG

    IPC: H01L31/0203

    CPC classification number: H01L31/0203 ,  B81B7/0077 ,  H01L23/10 ,  H01L24/97 ,  H01L27/14618 ,  H01L27/14683 ,  H01L2924/01005 ,  H01L2924/01021 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/00

    Abstract: According to an embodiment, a chip package is provided, which includes: a substrate having a first surface and a second surface; a device region formed in the substrate; a passivation layer formed overlying the first surface of the substrate; at least a polymer planarization layer formed overlying the passivation layer; a package substrate disposed overlying the first surface of the substrate; and a spacer layer disposed between the package substrate and the passivation layer, wherein the spacer layer and the package substrate surround a cavity overlying the substrate, wherein the polymer planar layer does not extends to an outer edge of the spacer layer.

    Abstract translation: 根据实施例，提供一种芯片封装，其包括：具有第一表面和第二表面的基板; 形成在所述基板中的器件区域; 形成在衬底的第一表面上的钝化层; 至少形成在所述钝化层上的聚合物平坦化层; 封装基板，设置在所述基板的第一表面上方; 以及间隔层，其设置在所述封装基板和所述钝化层之间，其中所述间隔层和所述封装基板围绕覆盖所述基板的空腔，其中所述聚合物平面层不延伸到所述间隔层的外边缘。

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