公开(公告)号：US20170207182A1

公开(公告)日：2017-07-20

申请号：US15409289

申请日：2017-01-18

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Tsang-Yu LIU ,  Chia-Sheng LIN ,  Chaung-Lin LAI

IPC: H01L23/00 ,  H01L23/18 ,  H01L21/78 ,  H01L21/54 ,  H01L21/52 ,  H01L23/055 ,  H01L21/48

CPC classification number: H01L23/562 ,  H01L21/4817 ,  H01L21/52 ,  H01L21/54 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/055 ,  H01L23/18 ,  H01L23/3114 ,  H01L23/522 ,  H01L24/16 ,  H01L25/065 ,  H01L27/14618 ,  H01L27/14687 ,  H01L2224/16237

Abstract: A chip package including a substrate is provided. The substrate has a first surface and a second surface opposite thereto. The substrate includes a sensing or device region which is adjacent to the first surface. A recess is in the substrate. The recess extends from the second surface towards the first surface, and vertically overlaps the sensing or device region. A redistribution layer is electrically connected to the sensing or device region, and extends from the second surface into the recess. A method of forming the chip package is also provided.

公开(公告)号：US20170012081A1

公开(公告)日：2017-01-12

申请号：US15181288

申请日：2016-06-13

Applicant: XINTEC INC.

Inventor： Chia-Lun SHEN ,  Yi-Ming CHANG ,  Hsiao-Lan YEH ,  Yen-Shih HO

IPC: H01L27/146 ,  H01L21/78 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L27/14687 ,  H01L21/78 ,  H01L24/03 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/94 ,  H01L25/0657 ,  H01L27/14636 ,  H01L2224/0331 ,  H01L2224/0332 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/06131 ,  H01L2224/06132 ,  H01L2224/06135 ,  H01L2224/11005 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1181 ,  H01L2224/11849 ,  H01L2224/13016 ,  H01L2224/13023 ,  H01L2224/13111 ,  H01L2224/1403 ,  H01L2224/14132 ,  H01L2224/14179 ,  H01L2224/16057 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/17135 ,  H01L2224/81011 ,  H01L2224/81191 ,  H01L2224/818 ,  H01L2224/81801 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06568 ,  H01L2924/3511 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A manufacturing method of a chip package includes the following steps. A patterned solder paste layer is printed on a patterned conductive layer of a wafer. Plural solder balls are disposed on the solder paste layer that is on a first portion of the conductive layer. A reflow process is performed on the solder balls and the solder paste layer. A flux layer converted from a surface of the solder paste layer is cleaned.

Abstract translation: 芯片封装的制造方法包括以下步骤。 将图案化的焊膏层印刷在晶片的图案化导电层上。 多个焊球设置在导电层的第一部分上的焊膏层上。 在焊球和焊膏层上进行回流处理。 从焊膏层的表面转换的焊剂层被清洁。

公开(公告)号：US20160315048A1

公开(公告)日：2016-10-27

申请号：US15138167

申请日：2016-04-25

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Shu-Ming CHANG ,  Hsing-Lung SHEN ,  Yu-Hao SU ,  Kuan-Jung WU ,  Yi CHENG

IPC: H01L23/522 ,  H01L23/48 ,  H01L21/768 ,  H01L21/288 ,  C25D17/08 ,  H01L49/02 ,  H01L21/673 ,  H01L21/677 ,  C25D17/00 ,  C25D7/12 ,  H01L27/144 ,  H01L21/3205

CPC classification number: H01L23/49838 ,  C25D17/001 ,  C25D17/005 ,  C25D17/06 ,  H01L21/2885 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/68721 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/5227 ,  H01L23/525 ,  H01L23/53214 ,  H01L23/53228 ,  H01L28/10 ,  H01L2224/11

Abstract: A semiconductor electroplating system includes a conducting ring and at least one conductive device. The conducting ring is used for carrying a wafer. The conducting ring has at least two connecting points. The wafer has a first surface and an opposite second surface. An isolation layer is located on the second surface. Two ends of the conductive device are respectively connected to the two connecting points of the conducting ring. When the conducting ring is immersed in the plating solution and is energized, a redistribution layer that is to be patterned is formed on the isolation layer. The conductive device is used for transmitting a partial current that passes through one of the connecting points to the other connecting point.

Abstract translation: 半导体电镀系统包括导电环和至少一个导电装置。 导电环用于承载晶片。 导电环具有至少两个连接点。 晶片具有第一表面和相对的第二表面。 隔离层位于第二表面上。 导电装置的两端分别连接到导电环的两个连接点。 当导电环浸入电镀溶液中并通电时，在隔离层上形成待图案化的再分配层。 导电装置用于将通过其中一个连接点的部分电流传送到另一个连接点。

公开(公告)号：US20160218133A1

公开(公告)日：2016-07-28

申请号：US15006052

申请日：2016-01-25

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Tsang-Yu LIU ,  Chi-Chang LIAO

IPC: H01L27/146

CPC classification number: H01L27/14618 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/14683 ,  H01L2224/16

Abstract: A method for forming a photosensitive module is provided. The method includes providing a sensing device. The sensing device includes a conducting pad located on a substrate. A first opening penetrates the substrate and exposes the conducting pad. A redistribution layer is in the first opening to electrically connect to the conducting pad. A cover plate is located on the substrate and covers the conducting pad. The method also includes removing the cover plate of the sensing device. The method further includes bonding the sensing device to a circuit board after the removal of the cover plate. The redistribution layer in the first opening is exposed and faces the circuit board. In addition, the method includes mounting an optical component corresponding to the sensing device on the circuit board. A photosensitive module formed by the method is also provided.

Abstract translation: 提供一种形成光敏模块的方法。 该方法包括提供感测装置。 感测装置包括位于基板上的导电垫。 第一开口穿透衬底并暴露导电垫。 再分布层位于第一开口中，以电连接到导电垫。 盖板位于基板上并覆盖导电垫。 该方法还包括移除感测装置的盖板。 该方法还包括在移除盖板之后将感测装置接合到电路板。 第一开口中的再分配层被暴露并面向电路板。 此外，该方法包括将对应于感测装置的光学部件安装在电路板上。 还提供了通过该方法形成的感光模块。

公开(公告)号：US20160141254A1

公开(公告)日：2016-05-19

申请号：US15008202

申请日：2016-01-27

Applicant: XINTEC INC.

Inventor： Yi-Min LIN ,  Yi-Ming CHANG ,  Shu-Ming CHANG ,  Yen-Shih HO ,  Tsang-Yu LIU ,  Chia-Ming CHENG

IPC: H01L23/552 ,  H01L23/544 ,  H01L23/00 ,  H01L21/78

CPC classification number: H01L23/552 ,  H01L21/4814 ,  H01L21/78 ,  H01L23/544 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L24/92 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2223/5446 ,  H01L2224/02313 ,  H01L2224/0235 ,  H01L2224/02371 ,  H01L2224/0239 ,  H01L2224/03614 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05571 ,  H01L2224/451 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/4847 ,  H01L2224/92 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/10156 ,  H01L2924/10157 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/01078 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2924/01013 ,  H01L2924/01047 ,  H01L2924/01022 ,  H01L2924/01074 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2924/014 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a first recess extending from the first surface towards the second surface; a second recess extending from a bottom of the first recess towards the second surface, wherein a sidewall and the bottom of the first recess and a second sidewall and a second bottom of the second recess together form an exterior side surface of the semiconductor substrate; a wire layer disposed over the first surface and extending into the first recess and/or the second recess; an insulating layer positioned between the wire layer and the semiconductor substrate; and a metal light shielding layer disposed over the first surface and having at least one hole, wherein a shape of the at least one hole is a quadrangle.

Abstract translation: 本发明的实施例提供一种芯片封装，其包括：具有第一表面和第二表面的半导体衬底; 从所述第一表面延伸到所述第二表面的第一凹部; 从所述第一凹部的底部朝向所述第二表面延伸的第二凹部，其中所述第一凹部的侧壁和所述底部以及所述第二凹部的第二侧壁和第二底部一起形成所述半导体衬底的外侧表面; 布置在所述第一表面上并延伸到所述第一凹部和/或所述第二凹部中的导线层; 位于所述导线层和所述半导体基板之间的绝缘层; 以及设置在所述第一表面上并且具有至少一个孔的金属遮光层，其中所述至少一个孔的形状是四边形。

公开(公告)号：US20150311175A1

公开(公告)日：2015-10-29

申请号：US14697235

申请日：2015-04-27

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Chih-Wei HO ,  Tsang-Yu LIU

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/498 ,  H01L25/00

CPC classification number: H01L23/49811 ,  B81B7/007 ,  B81B2207/093 ,  B81B2207/095 ,  B81B2207/096 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/13 ,  H01L23/49838 ,  H01L24/02 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/81 ,  H01L24/85 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02313 ,  H01L2224/0235 ,  H01L2224/02371 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05569 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06151 ,  H01L2224/06155 ,  H01L2224/06165 ,  H01L2224/1132 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/4801 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/81411 ,  H01L2224/81424 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81469 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/10156 ,  H01L2924/10157 ,  H01L2924/19107 ,  H01L2924/3512 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/81 ,  H01L2924/01029 ,  H01L2924/01013 ,  H01L2924/01079 ,  H01L2924/01078 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/85 ,  H01L2224/45099

Abstract: A stacked chip package is provided. The stacked chip package includes a first substrate having a first side and a second side opposite thereto. The first substrate includes a recess therein. The recess adjoins a side edge of the first substrate. A plurality of redistribution layers is disposed on the first substrate and extends onto the bottom of the recess. A second substrate is disposed on the first side of the first substrate. A plurality of bonding wires is correspondingly disposed on the redistribution layers in the recess, and extends onto the second substrate. A device substrate is disposed on the second side of the first substrate. A method of forming the stacked chip package is also provided.

Abstract translation: 提供堆叠的芯片封装。 堆叠的芯片封装包括具有第一侧和与其相对的第二侧的第一基板。 第一基板在其中包括凹部。 所述凹部邻接所述第一基板的侧边缘。 多个再分配层设置在第一基板上并延伸到凹部的底部。 第二基板设置在第一基板的第一侧上。 多个接合线相应地设置在凹部中的再分配层上并且延伸到第二基板上。 器件衬底设置在第一衬底的第二侧上。 还提供了形成堆叠芯片封装的方法。

公开(公告)号：US20150270236A1

公开(公告)日：2015-09-24

申请号：US14662151

申请日：2015-03-18

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Chia-Ming CHENG ,  Shu-Ming CHANG

IPC: H01L23/00

CPC classification number: H01L24/14 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L29/0657 ,  H01L2224/02233 ,  H01L2224/02313 ,  H01L2224/0235 ,  H01L2224/0236 ,  H01L2224/0237 ,  H01L2224/02371 ,  H01L2224/02375 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/14155 ,  H01L2224/14165 ,  H01L2924/014 ,  H01L2924/01029 ,  H01L2924/01013 ,  H01L2924/00014

Abstract: The present invention provides a chip package that includes a semiconductor chip, at least one recess, a plurality of first redistribution metal lines, and at least one protrusion. The semiconductor chip has a plurality of conductive pads disposed on an upper surface of the semiconductor chip. The recess extends from the upper surface to a lower surface of the semiconductor chip, and is arranged on the side of the semiconductor chip. The first redistribution metal lines are disposed on the upper surface, electrically connected to the conductive pad individually, and extended into the recesses separately. The protrusion is disposed in the recess and located between the adjacent first redistribution metal lines.

Abstract translation: 本发明提供了一种芯片封装，其包括半导体芯片，至少一个凹槽，多个第一再分布金属线以及至少一个突起。 半导体芯片具有设置在半导体芯片的上表面上的多个导电焊盘。 凹部从半导体芯片的上表面延伸到下表面，并且布置在半导体芯片的侧面上。 第一再分布金属线设置在上表面上，分别电连接到导电垫，并分别延伸到凹槽中。 突出部设置在凹部中并且位于相邻的第一再分布金属线之间。

公开(公告)号：US20150214162A1

公开(公告)日：2015-07-30

申请号：US14604525

申请日：2015-01-23

Applicant: XINTEC INC.

Inventor： Jiun-Yen LAI ,  Yu-Wen HU ,  Bai-Yao LOU ,  Chia-Sheng LIN ,  Yen-Shih HO ,  Hsin KUAN

IPC: H01L23/00

CPC classification number: H01L24/81 ,  H01L23/5227 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/48 ,  H01L28/10 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/03902 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05005 ,  H01L2224/05007 ,  H01L2224/05022 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05562 ,  H01L2224/05564 ,  H01L2224/05571 ,  H01L2224/05583 ,  H01L2224/05644 ,  H01L2224/13021 ,  H01L2224/1308 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13562 ,  H01L2224/13644 ,  H01L2224/48 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/014

Abstract: A manufacturing method of a passive component structure includes the following steps. A protection layer is formed on a substrate, and bond pads of the substrate are respectively exposed through protection layer openings. A conductive layer is formed on the bond pads and the protection layer. A patterned photoresist layer is formed on the conductive layer, and the conductive layer adjacent to the protection layer openings is exposed through photoresist layer openings. Copper bumps are respectively electroplated on the conductive layer. The photoresist layer and the conductive layer not covered by the copper bumps are removed. A passivation layer is formed on the copper bumps and the protection layer, and at least one of the copper bumps is exposed through a passivation layer opening. A diffusion barrier layer and an oxidation barrier layer are chemically plated in sequence on the copper bump.

Abstract translation: 无源元件结构的制造方法包括以下步骤。 保护层形成在基板上，并且基板的接合焊盘分别通过保护层开口露出。 在接合焊盘和保护层上形成导电层。 在导电层上形成图案化的光致抗蚀剂层，并且与保护层开口相邻的导电层通过光致抗蚀剂层开口露出。 铜凸块分别电镀在导电层上。 除去未被铜凸块覆盖的光致抗蚀剂层和导电层。 在铜凸块和保护层上形成钝化层，并通过钝化层开口露出至少一个铜凸块。 扩散阻挡层和氧化阻挡层依次化学镀在铜凸块上。

公开(公告)号：US20150097286A1

公开(公告)日：2015-04-09

申请号：US14568056

申请日：2014-12-11

Applicant: XINTEC INC.

Inventor： Wei-Luen SUEN ,  Chia-Sheng LIN ,  Yen-Shih HO ,  Tsang-Yu LIU

IPC: H01L23/00

CPC classification number: H01L24/17 ,  H01L21/6835 ,  H01L21/6836 ,  H01L22/12 ,  H01L22/20 ,  H01L24/02 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L27/14618 ,  H01L27/14636 ,  H01L2221/68327 ,  H01L2221/68386 ,  H01L2224/0231 ,  H01L2224/0235 ,  H01L2224/02377 ,  H01L2224/11002 ,  H01L2224/11312 ,  H01L2224/11334 ,  H01L2224/13012 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14131 ,  H01L2224/14145 ,  H01L2224/14177 ,  H01L2224/14179 ,  H01L2224/16058 ,  H01L2224/16227 ,  H01L2224/17051 ,  H01L2224/17517 ,  H01L2224/17519 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/81986 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/14146 ,  H01L2224/81 ,  H01L2224/81907 ,  H01L21/78 ,  H01L2924/00012 ,  H01L2224/11 ,  H01L2924/00014

Abstract: A chip package includes a packaging substrate, a semiconductor chip, and a plurality of conductive structures. The semiconductor chip has a central region and an edge region that surrounds the central region. The conductive structures are between the packaging substrate and the semiconductor chip. The conductive structures have different heights, and the heights of the conductive structures are gradually increased from the central region of the semiconductor chip to the edge region of the semiconductor chip, such that a distance between the edge region of the semiconductor chip and the packaging substrate is greater than a distance between the central region of the semiconductor chip and the packaging substrate.

Abstract translation: 芯片封装包括封装基板，半导体芯片和多个导电结构。 半导体芯片具有围绕中心区域的中心区域和边缘区域。 导电结构位于封装衬底和半导体芯片之间。 导电结构具有不同的高度，并且导电结构的高度从半导体芯片的中心区域逐渐增加到半导体芯片的边缘区域，使得半导体芯片的边缘区域与封装基板之间的距离 大于半导体芯片的中心区域和封装基板之间的距离。

公开(公告)号：US20150001710A1

公开(公告)日：2015-01-01

申请号：US14315163

申请日：2014-06-25

Applicant: XINTEC INC.

Inventor： Yi-Ming CHANG ,  Tsang-Yu LIU ,  Yen-Shih HO ,  Ying-Nan WEN

IPC: H01L23/00 ,  H01L23/31

CPC classification number: H01L23/3171 ,  H01L23/3114 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/48 ,  H01L2224/0231 ,  H01L2224/0235 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0361 ,  H01L2224/04042 ,  H01L2224/05007 ,  H01L2224/05026 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05184 ,  H01L2224/05548 ,  H01L2224/05562 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/0558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06155 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/10157 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A chip package is provided. The chip package includes a semiconductor chip, an isolation layer, a redistributing metal layer, and at least a bonding pad. The semiconductor chip includes at least one conducting disposed on a surface of the semiconductor chip. The isolation layer is disposed on the surface of the semiconductor chip, wherein the isolation layer has at least one first opening to expose the first conducting pad. The redistributing metal layer is disposed on the isolation layer and has at least a redistributing metal line corresponding to the conducting pad, the redistributing metal line is connected to the first conducting pad through the first opening. The bonding pad is disposed on the isolation layer and one side of the semiconductor chip, wherein the redistributing metal line extends to the bonding pad to electrically connect the conducting pad to the bonding pad.

Abstract translation: 提供芯片封装。 芯片封装包括半导体芯片，隔离层，再分布金属层和至少一个焊盘。 半导体芯片包括设置在半导体芯片的表面上的至少一个导体。 隔离层设置在半导体芯片的表面上，其中隔离层具有至少一个第一开口以暴露第一导电焊盘。 再分配金属层设置在隔离层上，并且至少具有对应于导电焊盘的再分布金属线，再分布金属线通过第一开口连接到第一导电焊盘。 接合焊盘设置在隔离层和半导体芯片的一侧，其中再分布金属线延伸到接合焊盘，以将导电焊盘电连接到接合焊盘。