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公开(公告)号：US20240315003A1
公开(公告)日：2024-09-19
申请号：US18675175
申请日：2024-05-28
发明人： Cheoljin CHO , Jaesoon LIM , Jaehyoung CHOI , Jungmin PARK
IPC分类号： H10B12/00
摘要： A capacitor and a DRAM device, the capacitor including a lower electrode; a dielectric layer structure on the lower electrode, the dielectric layer structure including a first zirconium oxide layer, a hafnium oxide layer, and a second zirconium oxide layer sequentially stacked; and an upper electrode on the dielectric layer structure, wherein the hafnium oxide layer has a tetragonal crystal phase or an orthorhombic crystal phase.
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公开(公告)号：US12088297B2
公开(公告)日：2024-09-10
申请号：US18320163
申请日：2023-05-18
发明人： Sasikanth Manipatruni , Yuan-Sheng Fang , Robert Menezes , Rajeev Kumar Dokania , Gaurav Thareja , Ramamoorthy Ramesh , Amrita Mathuriya
摘要： An adder with first and second majority gates. For a 1-bit adder, output from a 3-input majority gate is inverted and input two times to a 5-input majority gate. Other inputs to the 5-input majority gate are same as those of the 3-input majority gate. The output of the 5-input majority gate is a sum while the output of the 3-input majority gate is the carry. Multiple 1-bit adders are concatenated to form an N-bit adder. The input signals are driven to first terminals of non-ferroelectric capacitors while the second terminals are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a non-linear polar capacitor. The second terminal of the capacitor provides the output of the logic gate. A reset mechanism initializes the non-linear polar capacitor before addition function is performed.
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公开(公告)号：US12087810B2
公开(公告)日：2024-09-10
申请号：US17715389
申请日：2022-04-07
发明人： Jinhong Kim , Changsoo Lee , Yongsung Kim , Euncheol Do , Jooho Lee , Yong-Hee Cho
摘要： A capacitor including a lower electrode; an upper electrode apart from the lower electrode; and a between the lower electrode and the upper electrode, the dielectric including a dielectric layer including TiO2, and a leakage current reducing layer including GeO2 in the dielectric layer. Due to the leakage current reducing layer, a leakage current is effectively reduced while a decrease in the dielectric constant of the dielectric thin-film is small.
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公开(公告)号：US12057470B2
公开(公告)日：2024-08-06
申请号：US17809727
申请日：2022-06-29
发明人： Jungmin Park , Hanjin Lim , Hyungsuk Jung
CPC分类号： H01L28/55 , H01L28/65 , H01L28/75 , H10B12/482 , H01L28/82
摘要： A semiconductor device includes a capacitor. The capacitor includes a bottom electrode, a dielectric layer, and a top electrode that are sequentially stacked in a first direction. The dielectric layer includes a first dielectric layer and a second dielectric layer that are interposed between the bottom electrode and the top electrode and are stacked in the first direction. The first dielectric layer is anti-ferroelectric, and the second dielectric layer is ferroelectric. A thermal expansion coefficient of the first dielectric layer is greater than a thermal expansion coefficient of the second dielectric layer.
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公开(公告)号：US20240243164A1
公开(公告)日：2024-07-18
申请号：US18409957
申请日：2024-01-11
发明人： Jooho LEE , Yong-Hee CHO , Jinhong KIM , Changsoo LEE , Sung HEO
CPC分类号： H01L28/65 , H01L28/75 , H01L28/91 , H10B12/315
摘要： Provided are a capacitor, a method of preparing the capacitor, and an electronic device including the capacitor, the capacitor including a lower electrode, an upper electrode spaced apart from the lower electrode, a dielectric between the lower electrode and the upper electrode, a first layer between the lower electrode and the dielectric, and a second layer between the dielectric and the upper electrode, wherein the dielectric comprises TiO2 having a rutile phase and is doped with magnesium, the first layer includes a material having a higher work function than that of a material included in the lower electrode, and the second layer includes a dielectric protective material.
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6.发明公开公开(公告)号：US20240234031A1
公开(公告)日：2024-07-11
申请号：US18351171
申请日：2023-07-12
发明人： Narae HAN , Jeonggyu SONG , Beomseok KIM , Cheheung KIM , Haeryong KIM , Jooho LEE
CPC分类号： H01G4/10 , H01L28/60 , H01L28/65 , H01L29/511 , H01L29/517 , H01L29/94 , H10B12/31 , H01G4/008
摘要： A semiconductor device includes a first electrode, a second electrode spaced apart from the first electrode, a dielectric layer between the first electrode and the second electrode and including a metal oxide represented by MaOb, and a leakage current reducing layer on the dielectric layer between the first electrode and the second electrode and including an inorganic compound represented by Alx1Lx2Oy1Xy2, where a, b, M, L, X, x1, x2, y1, and y2 are as described in the description.
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7.发明公开公开(公告)号：US20240170212A1
公开(公告)日：2024-05-23
申请号：US18350600
申请日：2023-07-11
发明人： Jeonggyu SONG , Eunae CHO , Narae HAN , Beomseok KIM , Cheheung KIM , Jooho LEE , Wonsik CHOI
CPC分类号： H01G4/10 , H01L28/60 , H01L28/65 , H01L29/511 , H01L29/517 , H01L29/94 , H10B12/31 , H01G4/1236
摘要： A capacitor, a semiconductor device, and an electronic apparatus including the semiconductor device are disclosed. The capacitor includes a first electrode; a second electrode disposed apart from the first electrode; a dielectric film between the first electrode and the second electrode; and a leakage current reducing layer provided on the dielectric film between the first electrode and the second electrode and including MxAlyOz.
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公开(公告)号：US20240049450A1
公开(公告)日：2024-02-08
申请号：US18381119
申请日：2023-10-17
申请人： Intel Corporation
发明人： Travis W. LAJOIE , Abhishek A. SHARMA , Van H. LE , Chieh-Jen KU , Pei-Hua WANG , Jack T. KAVALIEROS , Bernhard SELL , Tahir GHANI , Gregory GEORGE , Akash GARG , Allen B. GARDINER , Shem OGADHOH , Juan G. ALZATE VINASCO , Umut ARSLAN , Fatih HAMZAOGLU , Nikhil MEHTA , Jared STOEGER , Yu-Wen HUANG , Shu ZHOU
CPC分类号： H10B12/315 , H01L27/1218 , H01L27/1222 , H01L27/1225 , H01L28/82 , H01L27/1248 , H01L27/1255 , H01L28/55 , H01L28/65 , H01L27/124 , H10B12/312 , H10B12/0335
摘要： Embodiments herein describe techniques for a semiconductor device including a substrate. A first capacitor includes a first top plate and a first bottom plate above the substrate. The first top plate is coupled to a first metal electrode within an inter-level dielectric (ILD) layer to access the first capacitor. A second capacitor includes a second top plate and a second bottom plate, where the second top plate is coupled to a second metal electrode within the ILD layer to access the second capacitor. The second metal electrode is disjoint from the first metal electrode. The first capacitor is accessed through the first metal electrode without accessing the second capacitor through the second metal electrode. Other embodiments may be described and/or claimed.
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公开(公告)号：US20240030277A1
公开(公告)日：2024-01-25
申请号：US18479271
申请日：2023-10-02
发明人： Jungmin PARK , Haeryong KIM , Young-Geun PARK
IPC分类号： H10B12/00
摘要： A semiconductor device includes a capacitor including a lower electrode an upper electrode, and a dielectric layer between the lower electrode and the upper electrode. The lower electrode includes ABO3 where ‘A’ is a first metal element and ‘B’ is a second metal element having a work function greater than that of the first metal element. The dielectric layer includes CDO3 where ‘C’ is a third metal element and ‘D’ is a fourth metal element. The lower electrode includes a first layer and a second layer which are alternately and repeatedly stacked. The first layer includes the first metal element and oxygen. The second layer includes the second metal element and oxygen. The dielectric layer is in contact with the lower electrode at a first contact surface the first contact surface corresponding to the second layer.
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公开(公告)号：US11855171B2
公开(公告)日：2023-12-26
申请号：US17400668
申请日：2021-08-12
发明人： Miin-Jang Chen , Sheng-Han Yi , Chen-Hsuan Lu
CPC分类号： H01L29/516 , H01L28/40 , H01L28/65 , H01L28/75 , H01L29/517 , H01L29/6684 , H01L29/78391
摘要： A method includes forming source/drain regions in a semiconductor substrate; depositing a zirconium-containing oxide layer over a channel region in the semiconductor substrate and between the source/drain region; forming a titanium oxide layer in contact with the zirconium-containing oxide layer; forming a top electrode over the zirconium-containing oxide layer, wherein no annealing is performed after depositing the zirconium-containing oxide layer and prior to forming the top electrode.
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