公开(公告)号：US20240330667A1

公开(公告)日：2024-10-03

申请号：US18738644

申请日：2024-06-10

申请人： Micron Technology, Inc.

发明人： Dmitri Yudanov ,  Sean S. Eilert ,  Hernan A. Castro ,  William A. Melton

IPC分类号： G06N3/063 ,  G06F3/06 ,  G06N3/04 ,  G11C7/06 ,  G11C8/08 ,  G11C11/54 ,  H03M1/46

CPC分类号： G06N3/063 ,  G06F3/0604 ,  G06F3/0661 ,  G06F3/0673 ,  G06N3/04 ,  G11C7/06 ,  G11C8/08 ,  G11C11/54 ,  H03M1/46

摘要： Methods, apparatuses, and systems for in- or near-memory processing are described. Bits of a first number may be stored on a number of memory elements, wherein each memory element of the number of memory elements intersects a digit line and an access line of a number of access lines. A number of signals corresponding to bits of a second number may be driven on the number of access lines to generate a number of output signals. A value equal to a product of the first number and the second number may be generated based on the number of output signals.

公开(公告)号：US12106823B2

公开(公告)日：2024-10-01

申请号：US17914845

申请日：2021-04-06

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Takeya Hirose ,  Seiichi Yoneda ,  Takayuki Ikeda ,  Shunpei Yamazaki

IPC分类号： G11C7/16 ,  G11C11/40 ,  G11C27/02 ,  H01L29/786 ,  G11C11/54

CPC分类号： G11C7/16 ,  G11C11/40 ,  G11C27/02 ,  H01L29/786 ,  G11C11/54

摘要： A semiconductor device capable of holding analog data is provided. Two holding circuits, two bootstrap circuits, and one source follower circuit are formed with use of four transistors and two capacitors. A memory node is provided in each of the two holding circuits; a data potential is written to one of the memory nodes and a reference potential is written to the other of the memory nodes. At the time of data reading, the potential of the one memory node is increased in one of the bootstrap circuits, and the potential of the other memory node is increased in the other of the bootstrap circuits. A potential difference between the two memory nodes is output by the source follower circuit. With use of the source follower circuit, the output impedance can be reduced.

公开(公告)号：US12094524B2

公开(公告)日：2024-09-17

申请号：US17162694

申请日：2021-01-29

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Avishek Biswas ,  Mahesh Madhukar Mehendale ,  Hetul Sanghvi

IPC分类号： G11C11/4094 ,  G06G7/16 ,  G06N3/065 ,  G11C5/06 ,  G11C7/10 ,  G11C11/4074 ,  G11C11/4097 ,  G11C11/4099 ,  G11C11/54

CPC分类号： G11C11/4094 ,  G06G7/16 ,  G06N3/065 ,  G11C5/06 ,  G11C7/1006 ,  G11C11/4074 ,  G11C11/4097 ,  G11C11/4099 ,  G11C11/54

摘要： A device includes a bit cell having first and second terminals, a first bit line coupled to the first terminal, a second bit line coupled to the second terminal, a first capacitor, a second capacitor, and a multiply and average (MAV) circuit coupled to the first capacitor, to the second capacitor, to the first bit line, and to the second bit line. The MAV circuit includes a first transistor coupled to the first capacitor and to a ground terminal and a second transistor coupled to the second capacitor and to the ground terminal. The first transistor has a first transistor control terminal selectively coupled to the first bit line and the second transistor has a second transistor control terminal selectively coupled to the second bit line.

公开(公告)号：US20240273349A1

公开(公告)日：2024-08-15

申请号：US18642669

申请日：2024-04-22

申请人： Micron Technology, Inc.

发明人： Dmitri Yudanov ,  Sean S. Eilert ,  Hernan A. Castro ,  Ameen D. Akel

IPC分类号： G06N3/063 ,  G06N3/049 ,  G06N3/084 ,  G06N5/046 ,  G11C11/4063 ,  G11C11/54

CPC分类号： G06N3/063 ,  G06N3/049 ,  G11C11/4063 ,  G11C11/54 ,  G06N3/084 ,  G06N5/046

摘要： Spiking events in a spiking neural network may be processed via a memory system. A memory system may store data corresponding to a group of destination neurons. The memory system may, at each time interval of a SNN, pass through data corresponding to a group of pre-synaptic spike events from respective source neurons. The data corresponding to the group of pre-synaptic spike events may be subsequently stored in the memory system.

公开(公告)号：US12062411B2

公开(公告)日：2024-08-13

申请号：US17732272

申请日：2022-04-28

申请人： SK hynix Inc. ,  Korea Advanced Institute of Science and Technology

发明人： Minki Jeong ,  Wanyeong Jung

IPC分类号： G11C16/10 ,  G11C7/10 ,  G11C7/12 ,  G11C11/54

CPC分类号： G11C7/1006 ,  G11C7/1048 ,  G11C7/12 ,  G11C11/54

摘要： A semiconductor device includes a cell block and a data block. The cell block includes an operation circuit having a first capacitor and a second capacitor and an input circuit configured to couple the first capacitor and the second capacitor to a bit line according to differential voltages provided via word lines and corresponding to a first data. The data block includes a capacitor array having a variable capacitance corresponding to a value of a second data; and a coupling switch configured to couple the bit line and the data block. The cell block and the data block may be used to perform a Multiply and Accumulate (MAC) operation.

公开(公告)号：US12061977B2

公开(公告)日：2024-08-13

申请号：US17675617

申请日：2022-02-18

申请人： Analog Devices, Inc.

发明人： Eric G. Nestler ,  Naveen Verma ,  Hossein Valavi

IPC分类号： G06N3/065 ,  G06N3/045 ,  G06N3/048 ,  G06N3/06 ,  G11C11/54

CPC分类号： G06N3/065 ,  G06N3/045 ,  G06N3/048 ,  G06N3/061 ,  G11C11/54

摘要： Systems and methods are provided for reducing power in in-memory computing, matrix-vector computations, and neural networks. An apparatus for in-memory computing using charge-domain circuit operation includes transistors configured as memory bit cells, transistors configured to perform in-memory computing using the memory bit cells, capacitors configured to store a result of in-memory computing from the memory bit cells, and switches, wherein, based on a setting of each of the switches, the charges on at least a portion of the plurality of capacitors are shorted together. Shorting together the plurality of capacitors yields a computation result.

公开(公告)号：US12057160B2

公开(公告)日：2024-08-06

申请号：US18123921

申请日：2023-03-20

申请人： Silicon Storage Technology, Inc. ,  The Regents of the University of California

发明人： Farnood Merrikh Bayat ,  Xinjie Guo ,  Dmitri Strukov ,  Nhan Do ,  Hieu Van Tran ,  Vipin Tiwari ,  Mark Reiten

IPC分类号： G11C11/00 ,  G06F3/06 ,  G06N3/04 ,  G06N3/045 ,  G06N3/063 ,  G11C11/54 ,  G11C16/08 ,  G11C16/12 ,  G11C16/16 ,  G11C16/34 ,  G11C29/38

CPC分类号： G11C11/54 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/0688 ,  G06N3/04 ,  G06N3/045 ,  G06N3/063 ,  G11C16/08 ,  G11C16/12 ,  G11C16/16 ,  G11C16/3436 ,  G11C29/38

摘要： Numerous examples of summing circuits for a neural network are disclosed. In one example, a circuit for summing current received from a plurality of synapses in a neural network comprises a voltage source; a load coupled between the voltage source and an output node; a voltage clamp coupled to the output node for maintaining a voltage at the output node; and a plurality of synapses coupled between the output node and ground; wherein an output current flows through the output node, the output current equal to a sum of currents drawn by the plurality of synapses.

公开(公告)号：US20240256847A1

公开(公告)日：2024-08-01

申请号：US18631003

申请日：2024-04-09

申请人： University of Dayton

发明人： Chris Yakopcic ,  Tarek M. Taha ,  Md Raqibul Hasan

IPC分类号： G06N3/065 ,  G06F17/10 ,  G06N3/045 ,  G06N3/08 ,  G11C11/54 ,  G11C13/00

CPC分类号： G06N3/065 ,  G06F17/10 ,  G06N3/045 ,  G06N3/08 ,  G11C11/54 ,  G11C13/0021 ,  G11C13/004

摘要： An analog neuromorphic circuit is disclosed having resistive memories that provide a resistance to each corresponding input voltage signal. Input voltages are applied to the analog neuromorphic circuit. Each input voltage represents a vector value that is a non-binary value included in a vector that is incorporated into a dot-product operation with weighted matrix values included in a weighted matrix. A controller pairs each resistive memory with another resistive memory. The controller converts each pair of resistance values to a single non-binary value. Each single non-binary value is mapped to a weighted matrix value included in the weighted matrix that is incorporated into the dot-product operation with the vector values included in the vector. The controller generates dot-product operation values from the dot-product operation with the vector and the weighted matrix where each dot-product operation is a non-binary value.

公开(公告)号：US20240194237A1

公开(公告)日：2024-06-13

申请号：US18534269

申请日：2023-12-08

申请人： Universty of Cincinnati

发明人： Siddharth Barve ,  Rashmi Jha

IPC分类号： G11C11/22 ,  G06N3/063 ,  G06N3/08 ,  G11C11/54 ,  H01L29/78

CPC分类号： G11C11/223 ,  G06N3/063 ,  G06N3/08 ,  G11C11/2275 ,  G11C11/54 ,  H01L29/78391

摘要： An apparatus may comprise a synapse comprising a first reconfigurable field-effect transistor; a second reconfigurable field-effect transistor connected in parallel to the first reconfigurable field-effect transistor; an input voltage applied to each of the first reconfigurable field-effect transistor and the second reconfigurable field-effect transistor corresponding to an input attribute associated with an error computation; and a current sensor measures a saturation drain current of the first reconfigurable field-effect transistor and the second reconfigurable field-effect transistor and determines a Euclidean error based on the saturation drain current of the FETs

公开(公告)号：US11978526B2

公开(公告)日：2024-05-07

申请号：US17705415

申请日：2022-03-28

申请人： Skymizer Taiwan Inc.

发明人： Shu-Ming Liu ,  Kai-Chiang Wu ,  Chien-Fa Chen ,  Wen Li Tang

IPC分类号： G11C29/44 ,  G11C11/54 ,  G11C29/00 ,  G11C29/42

CPC分类号： G11C29/4401 ,  G11C11/54 ,  G11C29/42 ,  G11C29/702

摘要： A data processing circuit and a fault mitigating method are provided. The method is adapted for a memory having at least one fault bit. The memory provides a block for data storage. A difference between an output of a value of a plurality of bits input to at least one computing layer in a neural network and a correct value is determined. The bits are respectively considered the at least one fault bit. A repair condition is determined based on the difference. The repair condition includes a correspondence between a position where the fault bit is located in the block and at least one non-fault bit in the memory. A value of at least one non-fault bit of the memory replaces a value of the fault bit based on the repair condition.