利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

134 条记录 (耗时 0.028 秒)

    Conductor interconnect with dendrites through film
    93.
    发明授权
    Conductor interconnect with dendrites through film 失效
    导体通过薄膜与树突互连

    公开(公告)号：US06300575B1

    公开(公告)日：2001-10-09

    申请号：US08918084

    申请日：1997-08-25

    申请人： Bernd K. Appelt ,  Saswati Datta ,  Michael A. Gaynes ,  John M. Lauffer ,  James R. Wilcox

    发明人： Bernd K. Appelt ,  Saswati Datta ,  Michael A. Gaynes ,  John M. Lauffer ,  James R. Wilcox

    IPC分类号： H05K114

    CPC分类号： H05K3/325 ,  H05K3/4614 ,  H05K2201/0373 ,  H05K2201/09536 ,  H05K2201/10666 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49165 ,  Y10T29/49194

    摘要： A method is provided for connecting two conductive layers in an electronic circuit package comprising the steps of forming dendrites on selected regions of a first conductive layer, forming dendrites on selected regions of a second conductive layer, applying an epoxy adhesive material over the first conductive layer, and compressively attaching the second conductive layer to the first conductive layer such that the dendrites on the first conductive layer contact the dendrites on the second conductive layer. Also claimed is an electronic circuit package incorporating the dendrites used for electrical interconnection manufactured in accordance with the present invention. An alternative embodiment of the invention utilizes an intermediate surface metal with dendrites in place of a “through via.”

    摘要翻译： 提供了一种用于连接电子电路封装中的两个导电层的方法，包括以下步骤：在第一导电层的选定区域上形成枝晶，在第二导电层的选定区域上形成枝晶，在第一导电层上施加环氧粘合剂材料 并且将第二导电层压缩附接到第一导电层，使得第一导电层上的枝晶与第二导电层上的枝晶接触。 还要求保护的是包括用于根据本发明制造的电互连的树突的电子电路封装。 本发明的替代实施例利用具有树突的中间表面金属代替“通孔”。

    Method for producing a circuit board with embedded decoupling capacitance
    94.
    发明授权
    Method for producing a circuit board with embedded decoupling capacitance 失效
    具有嵌入式去耦电容的印刷电路板的制造方法

    公开(公告)号：US06256850B1

    公开(公告)日：2001-07-10

    申请号：US09022258

    申请日：1998-02-11

    申请人： John M. Lauffer ,  Konstantinos Papathomas

    发明人： John M. Lauffer ,  Konstantinos Papathomas

    IPC分类号： H01G700

    CPC分类号： H05K1/162 ,  H05K3/429 ,  H05K3/4611 ,  H05K3/4641 ,  H05K2201/0209 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2203/0759 ,  Y10T29/43 ,  Y10T29/435

    摘要： A method is provided for producing a capacitor to be embedded in an electronic circuit package comprising the steps of selecting a first conductor foil, selecting a dielectric material, coating the dielectric material on at least one side of the first conductor foil, and layering the coated foil with a second conductor foil on top of the coating of dielectric material. Also claimed is an electronic circuit package incorporating at least one embedded capacitor manufactured in accordance with the present invention.

    摘要翻译： 提供了一种用于制造要嵌入电子电路封装的电容器的方法，包括以下步骤：选择第一导体箔，选择电介质材料，在第一导体箔的至少一侧上涂覆电介质材料， 在介质材料涂层的顶部具有第二导体箔的箔。 还要求保护的是包含至少一个根据本发明制造的嵌入式电容器的电子电路封装。

    Multi-voltage plane, multi-signal plane circuit card with photoimageable dielectric
    95.
    发明授权
    Multi-voltage plane, multi-signal plane circuit card with photoimageable dielectric 有权
    多电平面，多信号平面电路卡，带有可光成像电介质

    公开(公告)号：US06201194B1

    公开(公告)日：2001-03-13

    申请号：US09203978

    申请日：1998-12-02

    申请人： John M. Lauffer ,  Roy H. Magnuson ,  Voya R. Markovich ,  John A. Welsh

    发明人： John M. Lauffer ,  Roy H. Magnuson ,  Voya R. Markovich ,  John A. Welsh

    IPC分类号： H01R909

    CPC分类号： H05K3/429 ,  H01R12/523 ,  H05K3/0023 ,  H05K3/4602 ,  H05K3/4608 ,  H05K3/4641 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2203/0554 ,  Y10T29/49165

    摘要： A technique for forming an organic chip carrier or circuit board, having two voltage planes and at least two signal planes is provided which includes bonding a first layer of photolithographic dielectric material to a first metal layer and exposing the first layer of dielectric material to a pattern of radiation to provide at least one opening through the first layer of the dielectric material. A second metal layer is bonded to the first layer of photoimageable material on the opposite side from the first metal layer. Holes are etched in the first and second metal layers which correspond to and are larger than each of the patterns on said openings in the first layer of dielectric material. The exposed pattern on the first layer of dielectric material is then developed, with the openings in the first and second metal layers being larger than the corresponding developed opening in the first dielectric material. Second and third layers of photoimageable dielectric material are applied on the first and second metal layers, respectively and are photopatterned and developed to provide openings in each of the second and third layers of dielectric material some of which correspond to each of the holes in the first layer of dielectric material and the holes in the first and second metal layers, some of which terminate at the underlying metal layer. The exposed surfaces of both the second and third dielectric material, are circuitized and the holes plated or filled with metal.

    摘要翻译： 提供了一种用于形成具有两个电压平面和至少两个信号面的有机芯片载体或电路板的技术，其包括将第一层光刻电介质材料结合到第一金属层并将第一介电材料层暴露于图案 的辐射以提供通过电介质材料的第一层的至少一个开口。 第二金属层在与第一金属层相对的一侧上结合到可光成像材料的第一层。 在第一和第二金属层中蚀刻孔，其对应于并且大于第一介电材料层中的所述开口上的每个图案。 然后显影第一层介电材料上的暴露图案，其中第一和第二金属层中的开口大于第一介电材料中对应的显影开口。 将第二和第三层可光成像介电材料分别施加在第一和第二金属层上，并对其进行光刻图案化和显影以在第二和第三层介电材料中的每一个中提供开口，其中的第一和第三层对应于第一和第二金属层中的每个孔 介电材料层和第一和第二金属层中的孔，其中一些终止于下面的金属层。 第二和第三介电材料的暴露表面被电路化，并且孔被镀金或填充金属。

    Laminate substrate having joining layer of photoimageable material
    96.
    发明授权
    Laminate substrate having joining layer of photoimageable material 失效
    具有可光成像材料接合层的层叠基板

    公开(公告)号：US06195264B1

    公开(公告)日：2001-02-27

    申请号：US09195389

    申请日：1998-11-18

    申请人： John M. Lauffer ,  Heike Marcello ,  David J. Russell

    发明人： John M. Lauffer ,  Heike Marcello ,  David J. Russell

    IPC分类号： H05K118

    CPC分类号： H05K3/0061 ,  H01L21/4803 ,  H01L23/36 ,  H01L2924/0002 ,  H05K1/183 ,  H05K3/0023 ,  H05K3/386 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/53178 ,  Y10T156/1798 ,  H01L2924/00

    摘要： A cavity-type chip module. The module is formed with an adhesive joining layer of photoimageable material interposed between a metal stiffener and a laminate top layer with a central aperture defined in the top layer. The photoimageable material is exposed to actinic radiation, except for an area corresponding to the aperture in the top layer. The unexposed area of photoimageable material is developed away to form a window in the joining layer. The top layer, joining layer, and stiffener are laminated together with the window and aperture aligned, and with a portion of the stiffener spanning the aperture to define a cavity in the resulting substrate. The removal of the unexposed photoimageable material, and the selective exposure of the joining layer to actinic radiation, keep the cavity free of photoimageable material and inhibit bleeding of the photoimageable material into the cavity from its inner edge. As a result, a semiconductor component can be flush mounted in the cavity with optimal thermal conductivity to the metal stiffener.

    摘要翻译： 腔型芯片模块。 该模块形成有介于金属加强件和层压顶层之间的可光成像材料的粘合剂接合层，中间孔限定在顶层中。 光致成像材料暴露于光化辐射，除了对应于顶层中的孔的区域外。 可光成像材料的未曝光区域被开发出来以在接合层中形成窗口。 将顶层，接合层和加强件层压在一起，窗口和孔对齐，并且加强件的一部分跨越孔以在所得到的基底中限定空腔。 未曝光的可光成像材料的去除以及将接合层选择性地暴露于光化辐射，保持空腔不含可光成像的材料并且抑制可光成像材料从其内边缘渗入空腔。 结果，半导体部件可以齐平地安装在空腔中，对金属加强件具有最佳的导热性。

    Copper etching compositions, processes and products derived therefrom
    97.
    发明授权
    Copper etching compositions, processes and products derived therefrom 有权
    铜蚀刻组合物，由其衍生的工艺和产品

    公开(公告)号：US6156221A

    公开(公告)日：2000-12-05

    申请号：US165957

    申请日：1998-10-02

    申请人： John M. Lauffer ,  Kathleen L. Covert, deceased ,  Peter A. Moschak

    发明人： John M. Lauffer ,  Kathleen L. Covert, deceased ,  Peter A. Moschak

    IPC分类号： C23F1/18 ,  H05K3/06 ,  B44C1/22 ,  C09K13/00

    CPC分类号： C23F1/18 ,  H05K3/067 ,  Y10S428/901 ,  Y10T428/24917

    摘要： The present invention is a persulfate etchant composition especially useful for dissolving copper during fabrication of microelectronic packages. The etchant is characterized by its ability to selectively etch copper in the presence of nickel, nickel-phosphorous and noble metal alloys therefrom. Furthermore, no deleterious galvanic etching occurs in this etchant-substrate system so that substantially no undercutting of the copper occurs. The combination of high selectivity and no undercutting allows for a simplification of the microelectronic fabrication process and significant improvements in the design features of the microelectronic package, in particular higher density circuits. The persulfate etchant composition is stabilized with acid and phosphate salts to provide a process that is stable, fast acting, environmentally acceptable, has high capacity, and can be performed at room temperature. A preferred etchant composition is 230 gm/liter sodium persulfate, 3 volume % phosphoric acid and 0.058 molar sodium phosphate dibasic.

    摘要翻译： 本发明是在制造微电子封装期间特别可用于溶解铜的过硫酸盐蚀刻剂组合物。 蚀刻剂的特征在于其能够在镍，镍 - 磷和贵金属合金存在下选择性地蚀刻铜。 此外，在该蚀刻剂 - 衬底系统中不发生有害的电镀蚀刻，使得基本上不会发生铜的底切。 高选择性和无底切的组合允许微电子制造工艺的简化和微电子封装，特别是较高密度电路的设计特征的显着改进。 过硫酸盐蚀刻剂组合物用酸和磷酸盐稳定，以提供稳定，快速作用，环境可接受，具有高容量的方法，并且可以在室温下进行。 优选的蚀刻剂组合物为230gm / l过硫酸钠，3体积％磷酸和0.058摩尔磷酸氢二钠。

    Circuitized substrate utilizing three smooth-sided conductive layers as part thereof and electrical assemblies and information handling systems utilizing same
    99.
    发明授权
    Circuitized substrate utilizing three smooth-sided conductive layers as part thereof and electrical assemblies and information handling systems utilizing same 失效
    使用三个光滑侧导电层作为其一部分的电路基板和利用其的电组件和信息处理系统

    公开(公告)号：US08502082B2

    公开(公告)日：2013-08-06

    申请号：US11215206

    申请日：2005-08-31

    申请人： Benson Chan ,  John M. Lauffer

    发明人： Benson Chan ,  John M. Lauffer

    IPC分类号： H05K1/03 ,  H05K1/09

    CPC分类号： H05K3/4641 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/15311 ,  H05K3/383 ,  H05K2201/0355 ,  H05K2203/0353

    摘要： A circuitized substrate in which three conductive layers (e.g., electroplated copper foil) are bonded (e.g., laminated) to two dielectric layers. Each of the foil surfaces which physically bond to a respective dielectric layer are smooth (e.g., preferably by chemical processing) and may include a thin, organic layer thereon. One of the conductive layers may function as a ground or voltage (power) plane while the other two may function as signal planes with a plurality of individual signal lines as part thereof. An electrical assembly and an information handling system utilizing such a circuitized substrate are also provided, as is a method of making the substrate.

    摘要翻译： 其中三个导电层（例如，电镀铜箔）被结合（例如，层叠）到两个电介质层的电路化基板。 物理地结合到相应电介质层的每个箔表面是光滑的（例如优选通过化学处理），并且可以在其上包括薄的有机层。 导电层中的一个可以用作接地或电压（功率）面，而另外两个可以用作具有多条独立信号线作为其一部分的信号面。 还提供了利用这种电路化基板的电气组件和信息处理系统，以及制造基板的方法。