公开(公告)号：US20210317565A1

公开(公告)日：2021-10-14

申请号：US17196999

申请日：2021-03-09

Applicant: SPTS Technologies Limited

Inventor： Scott Haymore ,  Adrian Thomas ,  Steve Burgess

IPC: C23C14/16 ,  H03H3/08 ,  H03H9/02 ,  C23C14/35

Abstract: Sputter depositing a metallic layer on a substrate in the fabrication of a resonator device includes providing a magnetron sputtering apparatus comprising a chamber, a substrate support disposed within the chamber, a target made from a metallic material, and a plasma generating device, wherein the substrate support and the target are separated by a distance of 10 cm or less; supporting the substrate on the substrate support; performing a DC magnetron sputtering step that comprises sputtering the metallic material from the target onto the substrate so as to form a metallic layer on the substrate, wherein during the DC magnetron sputtering step the chamber has a pressure of at least 6 mTorr of a noble gas, the target is supplied with a power having a power density of at least 6 W/cm2, and the substrate has a temperature in the range of 200-600° C.

公开(公告)号：US20210183703A1

公开(公告)日：2021-06-17

申请号：US17094759

申请日：2020-11-10

Applicant: SPTS Technologies Limited

Inventor： Matthew Michael Day ,  Samira Binte Kazemi

IPC: H01L21/78 ,  H01L21/683 ,  H01L21/67

Abstract: A semiconductor wafer dicing process is disclosed for dicing a wafer into individual dies. Scribe lines are formed within a polymer coating to expose regions of wafer to form a pre-processed product. The pre-processed product within the chamber is plasma etched to remove the exposed regions of the wafer to separate the individual dies and form a processed product. A frame cover is then removed and the processed product, wafer frame and adhesive tape are exposed to an oxygen plasma within the chamber to partially remove an outermost region of the polymer coating, which is most heavily contaminated with fluorine, to leave a residual polymer coating on the individual dies and form a post-processed product. The residual polymer coating on the individual dies of the post-processed product is then removed.

公开(公告)号：US20210082722A1

公开(公告)日：2021-03-18

申请号：US16919180

申请日：2020-07-02

Applicant: SPTS Technologies Limited

Inventor： Attila Nagy ,  Kris Martin

IPC: H01L21/67 ,  H01L21/677 ,  H01L21/68

Abstract: A wafer processing system has a transport vacuum chamber for handling a frame assembly under vacuum conditions, at least one vacuum cassette elevator load lock for housing a cassette and adjusting a vertical position of the cassette under vacuum conditions, and at least one wafer processing module in vacuum communication with the transport vacuum chamber. An actuating assembly changes guide members from an expanded configuration to a contracted configuration to reduce a first cross-sectional dimension of a frame assembly receiving area and to reduce a second cross-sectional dimension of the frame assembly receiving area that is perpendicular to the first cross-sectional dimension.

公开(公告)号：US20200325588A1

公开(公告)日：2020-10-15

申请号：US16845487

申请日：2020-04-10

Applicant: SPTS Technologies Limited

Inventor： Martin Ayres ,  John MacNeil ,  Trevor Thomas

IPC: C25D5/00 ,  C25D7/12 ,  C25D17/00 ,  C25D21/10 ,  C25D21/12

Abstract: An apparatus for electrochemically processing a semiconductor substrate includes a processing chamber of the type that is sealable to a peripheral portion of a semiconductor substrate so as to define a covered processing volume. The semiconductor substrate is supported by a substrate support. A magnetic arrangement is disposed outside of the processing chamber and produces a magnetic field. The magnetic field is changed using a controller for controlling the magnetic arrangement. An agitator is disposed within the processing chamber. The agitator comprises a magnetically responsive element which is responsive to changes in the magnetic field of the magnetic arrangement so as to provide a reciprocating motion to the agitator.

公开(公告)号：US10601388B2

公开(公告)日：2020-03-24

申请号：US15286283

申请日：2016-10-05

Applicant: SPTS TECHNOLOGIES LIMITED

Inventor： Stephen R Burgess ,  Rhonda Hyndman ,  Amit Rastogi ,  Scott Haymore ,  Constanine Fragos

IPC: H02H3/02 ,  C23C14/00 ,  C23C14/34 ,  C23C14/06 ,  C23C14/14 ,  H03H9/02 ,  H03H3/02

Abstract: A method is for depositing by pulsed DC reactive sputtering an additive containing aluminium nitride film containing at least one additive element selected from Sc, Y, Ti, Cr, Mg and Hf. The method includes depositing a first layer of the additive containing aluminium nitride film onto a film support by pulsed DC reactive sputtering with an electrical bias power applied to the film support. The method further includes depositing a second layer of the additive containing aluminium nitride film onto the first layer by pulsed DC reactive sputtering with no electrical bias power applied to the film support or with an electrical bias power applied to the film support which is lower than the electrical bias power applied during the sputter deposition of the first layer, where the second layer has the same composition as the first layer.

公开(公告)号：US20200090913A1

公开(公告)日：2020-03-19

申请号：US16541635

申请日：2019-08-15

Applicant: SPTS Technologies Limited

Inventor： TONY WILBY ,  STEVE BURGESS ,  ADRIAN THOMAS ,  RHONDA HYNDMAN ,  SCOTT HAYMORE ,  VLIVE WIDDICKS ,  IAN MONCRIEFF

IPC: H01J37/34 ,  C23C14/35 ,  C23C14/54

Abstract: A magnet assembly is disclosed for steering ions used in the formation of a material layer upon a substrate during a pulsed DC physical vapour deposition process. Apparatus and methods are also disclosed incorporating the assembly for controlling thickness variation in a material layer formed via pulsed DC physical vapour deposition. The magnet assembly comprises a magnetic field generating arrangement for generating a magnetic field proximate the substrate and means for rotating the ion steering magnetic field generating arrangement about an axis of rotation, relative to the substrate. The magnetic field generating arrangement comprises a plurality of magnets configured to an array which extends around the axis of rotation, wherein the array of magnets are configured to generate a varying magnetic field strength along a radial direction relative to the axis of rotation.

公开(公告)号：US20190267962A1

公开(公告)日：2019-08-29

申请号：US16129346

申请日：2018-09-12

Applicant: SPTS Technologies Limited

Inventor： RHONDA HYNDMAN ,  STEVE BURGESS

IPC: H03H3/10 ,  H03H9/02 ,  H03H9/25 ,  H03H9/64 ,  H03H9/145 ,  C23C14/35 ,  C23C14/34 ,  C23C14/08

Abstract: A method of reducing non-uniformity in the resonance frequencies of a surface acoustic wave (SAW) device, the SAW device comprising a silicon oxide layer comprising an oxide of silicon deposited over interdigital transducers on a piezoelectric substrate by reactive sputtering. The method comprises positioning a piezoelectric substrate having interdigital transducers on a substrate support, then depositing a silicon oxide layer comprising an oxide of silicon over the piezoelectric substrate and the interdigital transducers to form a SAW device. The substrate support is positioned relative to a sputtering target so that the silicon oxide layer of the SAW device has an arithmetic mean surface roughness (Ra) of 11 angstroms or less.

公开(公告)号：US10366899B2

公开(公告)日：2019-07-30

申请号：US15626250

申请日：2017-06-19

Applicant: SPTS TECHNOLOGIES LIMITED

Inventor： Oliver J Ansell ,  David A Tossell ,  Gautham Ragunathan

IPC: H01S5/02 ,  H01L41/338 ,  H01L21/78 ,  H01L21/683 ,  H01L21/67 ,  H01L21/66 ,  H01L21/3213 ,  H01L21/3065 ,  H01J37/32

Abstract: A method is for detecting a condition associated with a final phase of a plasma dicing process. The method includes providing a non-metallic substrate having a plurality of dicing lanes defined thereon, plasma etching through the substrate along the dicing lanes, wherein during the plasma etching infrared emission emanating from at least a portion of the dicing lanes is monitored so that an increase in infrared emission from the dicing lanes is observed as the final phase of the plasma dicing operation is entered, and detecting the condition associated with the final phase of the plasma dicing from the monitored infrared emission.

公开(公告)号：US10079150B2

公开(公告)日：2018-09-18

申请号：US14807399

申请日：2015-07-23

Applicant: SPTS Technologies Limited

Inventor： John Joseph Neumann, Jr. ,  Kyle Stanton Lebouitz

IPC: H01L21/302 ,  H01L21/306 ,  H01L21/311 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/308 ,  H01L21/67

CPC classification number: H01L21/30604 ,  H01L21/0212 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/31116 ,  H01L21/32135 ,  H01L21/67069

Abstract: According to the invention there is provided a method of dry gas phase chemically etching a structure comprising the steps of: positioning the structure in an etch chamber, the structure comprising a first material and a second material, wherein the first material is selected from silicon, molybdenum, germanium, SiGe and tungsten, the second material is silicon dioxide or silicon nitride, and at least one surface of the first material is exposed so as to be contactable by a gas phase chemical etchant; etching the first material with a noble gas fluoride or halogen fluoride gas phase chemical etchant; and exposing the etch chamber to water vapour so that the step of etching the first material is performed in the presence of water vapour.

公开(公告)号：US20180211856A1

公开(公告)日：2018-07-26

申请号：US15876300

申请日：2018-01-22

Applicant: SPTS Technologies Limited

Inventor： JOHN MACNEIL ,  MARTIN AYRES ,  TREVOR THOMAS

IPC: H01L21/67 ,  H01L21/677 ,  H01L21/687 ,  C25D17/00 ,  C25D17/06

CPC classification number: H01L21/67196 ,  C25D17/001 ,  C25D17/004 ,  C25D17/06 ,  H01L21/2885 ,  H01L21/67178 ,  H01L21/6719 ,  H01L21/6723 ,  H01L21/67766 ,  H01L21/67769 ,  H01L21/67778 ,  H01L21/68707

Abstract: An apparatus for processing a front face of a semiconductor wafer is provided. The apparatus includes a main chamber, at least one loading port connected to the main chamber for introducing the wafer to the main chamber, at least one stack of wafer processing modules, and a transfer mechanism for transferring the wafer between the loading port and the processing modules. The at least one stack of wafer processing modules includes three or more substantially vertically stacked wafer processing modules, wherein adjacent wafer processing modules in the stack have a vertical separation of less than 50 cm, and each processing module is configured to process the wafer when disposed substantially horizontally therein with the front face of the wafer facing upwards, and at least one wafer processing module is an electrochemical wafer processing module.