公开(公告)号：US20240334850A1

公开(公告)日：2024-10-03

申请号：US18741808

申请日：2024-06-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Jen Wang ,  Chun-Hung Cheng ,  Chuan-Fu Wang

IPC: H10N70/00 ,  H10B63/00

CPC classification number: H10N70/8833 ,  H10B63/00 ,  H10N70/023 ,  H10N70/063 ,  H10N70/841

Abstract: A resistive random access memory (RRAM) structure includes a RRAM cell, spacers and a dielectric layer. The RRAM cell is disposed on a substrate. The spacers are disposed beside the RRAM cell, wherein widths of top surfaces of the spacers are larger than or equal to widths of bottom surfaces of the spacers. The dielectric layer blanketly covers the substrate and sandwiches the RRAM cell, wherein the spacers are located in the dielectric layer. A method for forming the resistive random access memory (RRAM) structure is also provided.

公开(公告)号：US20240332086A1

公开(公告)日：2024-10-03

申请号：US18739261

申请日：2024-06-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Fan Li ,  Po-Ching Su ,  Yu-Fu Wang ,  Min-Hua Tsai ,  Ti-Bin Chen ,  Chih-Chiang Wu ,  Tzu-Chin Wu

IPC: H01L21/8234 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L21/823437 ,  H01L21/823462 ,  H01L21/823481 ,  H01L29/4232 ,  H01L29/78

Abstract: A method for fabricating a semiconductor device includes the steps of forming a metal gate on a substrate, a spacer around the metal gate, and a first interlayer dielectric (ILD) layer around the spacer, performing a plasma treatment process to transform the spacer into a first bottom portion and a first top portion, performing a cleaning process to remove the first top portion, and forming a second ILD layer on the metal gate and the first ILD layer.

公开(公告)号：US12108691B2

公开(公告)日：2024-10-01

申请号：US18324173

申请日：2023-05-26

Applicant: United Microelectronics Corp.

Inventor： Chich-Neng Chang ,  Da-Jun Lin ,  Shih-Wei Su ,  Fu-Yu Tsai ,  Bin-Siang Tsai

IPC: H10N70/20 ,  H10B63/00 ,  H10N70/00

CPC classification number: H10N70/24 ,  H10B63/30 ,  H10N70/063 ,  H10N70/826 ,  H10N70/841

Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes a device substrate, a resistance variable layer and a top electrode. The bottom electrode is disposed on the device substrate. The resistance variable layer is disposed on the bottom electrode. The top electrode is disposed on the resistance variable layer. The bottom electrode is formed with a tensile stress, while the top electrode is formed with a compressive stress.

公开(公告)号：US12107157B2

公开(公告)日：2024-10-01

申请号：US18223543

申请日：2023-07-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kai-Lin Lee ,  Zhi-Cheng Lee ,  Wei-Jen Chen

IPC: H01L29/778 ,  H01L21/02 ,  H01L21/20 ,  H01L21/308 ,  H01L29/20 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/308 ,  H01L29/2003 ,  H01L29/66462

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; removing the hard mask to form a first recess for exposing the barrier layer; removing the hard mask adjacent to the first recess to form a second recess; and forming a p-type semiconductor layer in the first recess and the second recess.

公开(公告)号：US12107151B2

公开(公告)日：2024-10-01

申请号：US18208895

申请日：2023-06-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Jung Chuang ,  Tsuo-Wen Lu ,  Chia-Ming Kuo ,  Po-Jen Chuang ,  Chi-Mao Hsu

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L21/311

CPC classification number: H01L29/6656 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02255 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/31116

Abstract: A semiconductor device includes a gate structure on a substrate, a first spacer on sidewalls of gate structure, a second spacer on sidewalls of the first spacer, a polymer block adjacent to the first spacer and on a corner between the gate structure and the substrate, an interfacial layer under the polymer block, and a source/drain region adjacent to two sides of the first spacer. Preferably, the polymer block is surrounded by the first spacer, the interfacial layer, and the second spacer.

公开(公告)号：US20240324472A1

公开(公告)日：2024-09-26

申请号：US18679437

申请日：2024-05-30

Applicant: United Microelectronics Corp.

Inventor： Hui-Lin Wang ,  Yu-Ping Wang ,  Chen-Yi Weng ,  Chin-Yang Hsieh ,  Si-Han Tsai ,  Che-Wei Chang ,  Jing-Yin Jhang

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01 ,  H10N50/85

CPC classification number: H10N50/80 ,  H10B61/00 ,  H10N50/01 ,  H10N50/85

Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses.

公开(公告)号：US20240321973A1

公开(公告)日：2024-09-26

申请号：US18138728

申请日：2023-04-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Hua Yang ,  Chih-Chien CHANG ,  Shen-De WANG ,  JIANJUN YANG ,  Wei Ta ,  Yuan-Hsiang Chang

IPC: H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H10B41/35

CPC classification number: H01L29/404 ,  H01L29/401 ,  H01L29/66681 ,  H01L29/66825 ,  H01L29/7816 ,  H10B41/35

Abstract: A power metal-oxide-semiconductor structure includes a semiconductor substrate, a gate electrode disposed above the semiconductor substrate, a field plate, and an electrically conductive pattern. The gate electrode and the field plate are disposed above the semiconductor substrate, the electrically conductive pattern is disposed between the field plate and the semiconductor substrate in a vertical direction, and the field plate and the electrically conductive pattern are located at the same side of the gate electrode in a horizontal direction. A manufacturing method of a power metal-oxide-semiconductor structure includes the following steps. The electrically conductive pattern and the field plate are formed above a first region of the semiconductor substrate. Subsequently, the gate electrode is formed above the first region of the semiconductor substrate.

公开(公告)号：US20240313046A1

公开(公告)日：2024-09-19

申请号：US18134555

申请日：2023-04-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Guang-Yu Lo ,  Chun-Tsen Lu ,  Chung-Fu Chang ,  Chih-Shan Wu ,  Yu-Hsiang Lin ,  Wei-Hao Chang

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0649 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method for fabricating a semiconductor device includes the steps of forming a fin-shaped structure on a substrate, forming a first trench and a second trench in the fin-shaped structure, forming a first dielectric layer in the first trench and the second trench, removing part of the first dielectric layer, forming a second dielectric layer in the first trench and the second trench to form a first single diffusion break (SDB) structure and a second SDB structure, and then forming a gate structure on the fin-shaped structure, the first SDB structure, and the second SDB structure.

公开(公告)号：US20240312527A1

公开(公告)日：2024-09-19

申请号：US18677836

申请日：2024-05-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Ning Peng ,  Hsueh-Chun Hsiao ,  Tzu-Yun Chang

IPC: G11C16/24 ,  G11C16/08 ,  H01L29/788 ,  H10B41/10 ,  H10B41/27

CPC classification number: G11C16/24 ,  G11C16/08 ,  H01L29/7881 ,  H10B41/10 ,  H10B41/27

Abstract: A method for forming semiconductor structure with wave shaped erase gate, the method including the steps: forming a floating gate having staggered islands on a substrate, forming a erase gate having a wave shape on the substrate at a first side of the floating gate, and forming a word line having the wave shape on the substrate at a second side of the floating gate opposite to the first side.

公开(公告)号：US12096635B2

公开(公告)日：2024-09-17

申请号：US17722403

申请日：2022-04-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yung-Ting Chen ,  Hsueh-Chun Hsiao

IPC: H10B43/30 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792

CPC classification number: H10B43/30 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

Abstract: An SONOS memory cell includes a silicon substrate. A tunnel silicon oxide layer, a silicon nitride layer and a silicon oxide layer are disposed from bottom to top on the silicon substrate. The silicon oxide layer includes two first silicon oxide layers and a second silicon oxide layer. A thickness of the silicon oxide layer is smaller than a thickness of each of the first silicon oxide layers. A control gate covers and contacts the silicon oxide layer. A first source/drain doping region and a second source/drain doping region are respectively disposed at two sides of the control gate. The silicon oxide layer has a cross section. The second silicon oxide layer is sandwiched between the two first silicon oxide layers on the cross section.